85408I IDT | Alldatasheet

Document overview

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Technical content

Features

  • Eight differential LVDS output pairs
  • One differential clock input pair
  • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 700MHz
  • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
  • Translates any single-ended input signal to LVDS with resistor bias on nCLK input
  • Multiple output enable inputs for disabling unused outputs in reduced fanout applications
  • Additive phase jitter, RMS: 167fs (typical)
  • Output skew: 50ps (maximum)
  • Part-to-part skew: 550ps (maximum)
  • Propagation delay: 2.4ns (maximum)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package nQ6 nQ5 nQ4 nQ3 nQ2 nQ1 nQ7 GND OE V DD VDD GND VDD CLK nCLK nQ0 CLK nCLK OE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 Pin Assignment 85408I 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View Block Diagram Low Skew , 1-to-8, Differential-to-LVDS Clock 85408I Datasheet

Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ6, Q6 Output Differential out put pair. LVDS interface levels. 3, 4 nQ5, Q5 Output Differential out put pair. LVDS interface levels. 5, 6 nQ4, Q4 Output Differential out put pair. LVDS interface levels. 7, 8 nQ3, Q3 Output Differential out put pair. LVDS interface levels. 9, 10 nQ2, Q2 Output Differential out put pair. LVDS interface levels. 11, 12 nQ1, Q1 Output Differential out put pair. LVDS interface levels. 13, 14 nQ0, Q0 Output Differential out put pair. LVDS interface levels. 15 nCLK Input Pullup Inverting differential clock input. 16 CLK Input Pulldown Non-inverting differential clock input. 17, 19, 20 V DD Power Positive supply pins. 18, 21 GND Power Power supply ground.

22 OE Input Pullup

23, 24 nQ7, Q7 Output Differential out put pair. LVDS interface levels.

3©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016 85408I Datasheet Function Tables Table 3A. Output Enable Function Table Table 3B. Clock Input Function Table NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels. Inputs Outputs OE Q[0:7], nQ[0:7]

0 High-Impedance

1 Active (default)

Input to Output Mode PolarityCLK nCLK Q[0:7] nQ[0:7] 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-E nded to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single- Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single- Ended to Differential Inverting

4©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016 85408I Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics,VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 70°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 90 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current V DD = VIN = 3.465V 5 µA IIL Input Low Current V DD = 3.465V, VIN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK V DD = VIN = 3.465V 150 µA nCLK V DD = VIN = 3.465V 5 IIL Input Low Current CLK V DD = 3.465V, VIN = 0V -5 µA nCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V

Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. point of the input to the differential output crossing point. the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

6©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016 85408I Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) Additive Phase Jitter @156.25MHz 12kHz – 20MHz = 167fs (typical)

7©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016 85408I Datasheet Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Propagation Delay Output Skew Differential Input Level Part-to-Part Skew Output Duty Cycle/Pulse Width/Period GND VDD tPD Q[0:7] nQ[0:7] nCLK CLK Qx nQx Qy nQy VDD nCLK CLK GND V CMR Cross Points VPP tsk(pp) Part 1 Part 2 Qx nQx Qy nQy Q[0:7] nQ[0:7]

8©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016 85408I Datasheet Parameter Measurement Information, continued Output Rise/Fall Time Differential Output Voltage Setup Differential Output Short Circuit Setup Offset Voltage Setup Power Off Leakage Setup Output Short Circuit Current Setup 20% 80% 80% 20% tR tF VOD Q[0:7] nQ[0:7] out out LVDSDC Input IOSD VDD LVDS IOFF VDD out LVDSDC Input IOS IOSB VDD out

This section provides information on power dissipation and junction temperature for the 85408I. Equations and example calculations are also provided. following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. maximum recommended junction temperature for devices is 125°C. a multi-layer board, the appropriate value is 70°C/W per Table 6 below. Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection

Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP

14©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016 85408I Datasheet

Ordering Information

Table 9. Ordering Information

15©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016 85408I Datasheet Revision History Sheet Rev Table Page Description of Change Date A 1 Pin Assignment - corrected package information from 300-MIL to 173-MIL. 8/25/04 A T8 Features Section - added Lead-Free bullet. Corrected Block Diagram. Ordering Information Table - added Lead-Free information. 4/25/05 B T5 5 AC Characteristics Table - added Additive Phase Jitter spec. Added Additive Phase Jitter Plot. Added Power Considerations section. Converted datasheet format. 6/25/09 B T9 1 Features section - removed reference to leaded devices. Removed ICS Chip logo from General description. Ordering Information - removed leaded devices. Updated datasheet format. 3/5/15 C Deleted "HiperClockS" reference throughout the datasheet. Updated datasheet header/footer. 2/23/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licen ses are implied. This product is intended for use in normal commercial applications. Any other app lications, such as those requiring extended temperature ranges, high reliability or other extraordinary envi ronmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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