85408

85408_15 IDT | Alldatasheet

Document overview

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• PDF pages: 16

Technical content

Features

• Eight differential LVDS output pairs
• CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 550ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package nQ6 nQ5 nQ4 nQ3 nQ2 nQ1 nQ7 GND OE V DD VDD GND VDD CLK nCLK nQ0 CLK nCLK OE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 Pin Assignment 85408 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View Block Diagram

85408 DATA SHEET

Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ6, Q6 Output Differential out put pair. LVDS interface levels. 3, 4 nQ5, Q5 Output Differential out put pair. LVDS interface levels. 5, 6 nQ4, Q4 Output Differential out put pair. LVDS interface levels. 7, 8 nQ3, Q3 Output Differential out put pair. LVDS interface levels. 9, 10 nQ2, Q2 Output Differential out put pair. LVDS interface levels. 11, 12 nQ1, Q1 Output Differential out put pair. LVDS interface levels. 13, 14 nQ0, Q0 Output Differential out put pair. LVDS interface levels. 15 nCLK Input Pullup Inverting differential clock input. 16 CLK Input Pulldown Non-inverting differential clock input. 17, 19, 20 V DD Power Positive supply pins. 18, 21 GND Power Power supply ground.

22 OE Input Pullup

23, 24 nQ7, Q7 Output Differential out put pair. LVDS interface levels.

0 High-Impedance

1 Active (default)

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK 3 Rev C 1/5/15 Table 3B. Clock Input Function Table NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels. Inputs Outputs Input to Output Mode PolarityCLK nCLK Q[0:7] nQ[0:7] 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting

Rev C 1/5/15 4 LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics,VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 70°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 90 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current V DD = VIN = 3.465V 5 µA IIL Input Low Current V DD = 3.465V, VIN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK V DD = VIN = 3.465V 150 µA nCLK V DD = VIN = 3.465V 5 IIL Input Low Current CLK V DD = 3.465V, VIN = 0V -5 µA nCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V

Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. NOTE: All parameters measured at f 622MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. point of the input to the differential output crossing point. the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

Rev C 1/5/15 6 LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) Additive Phase Jitter @156.25MHz 12kHz – 20MHz = 167fs (typical)

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK 7 Rev C 1/5/15 Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Propagation Delay Output Skew Differential Input Level Part-to-Part Skew Output Duty Cycle/Pulse Width/Period GND VDD tPD Q[0:7] nQ[0:7] nCLK CLK Qx nQx Qy nQy VDD nCLK CLK GND V CMR Cross Points VPP tsk(pp) Part 1 Part 2 Qx nQx Qy nQy Q[0:7] nQ[0:7]

Rev C 1/5/15 8 LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK Parameter Measurement Information, continued Output Rise/Fall Time Differential Output Voltage Setup Differential Output Short Circuit Setup Offset Voltage Setup Power Off Leakage Setup Output Short Circuit Current Setup 20% 80% 80% 20% tR tF VOD Q[0:7] nQ[0:7] out out LVDSDC Input IOSD VDD LVDS IOFF VDD out LVDSDC Input IOS IOSB VDD out

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK 9 Rev C 1/5/15

Application Information

Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 1. Single-Ended Signal Driving Differential Input

Rev C 1/5/15 10 LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 2A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 2B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver 50Ω 50Ω 1.8V Zo = 50Ω Zo = 50Ω CLK nCLK 3.3V LVHSTL IDT LVHSTL Driver Differential Input HCSL *R3 *R4 CLK nCLK 3.3V 3.3V Differential Input CLK nCLK Differential Input SSTL 2.5V Zo = 60Ω Zo = 60Ω 2.5V 3.3V 120Ω 120Ω 120Ω 120Ω

Figure 3. In a 100 differential recommended to terminate the unused outputs. Figure 3. Typical LVDS Driver Termination

This section provides information on power dissipation and junction temperature for the 85408. Equations and example calculations are also provided. following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. maximum recommended junction temperature for HiPerClockS devices is 125°C. a multi-layer board, the appropriate value is 70°C/W per Table 6 below. Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection

Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP Table 8. Package Dimensions

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK 14 Rev C 1/5/15

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK 15 Rev C 1/5/15 Rev Table Page Description of Change Date A Reliability Table - revised air flow from Linear Feet per Minute to Meters per Second. ICS85408BG. 5/6/04 A 1 Pin Assignment - corrected package information from 300-MIL to 173-MIL. 8/25/04 A T8 Features Section - added Lead-Free bullet. Corrected Block Diagram. Ordering Information Table - added Lead-Free information. 4/25/05 B T5 5 AC Characteristics Table - added Additive Phase Jitter spec. Added Additive Phase Jitter Plot. Added Power Considerations section. Converted datasheet format. 6/24/09 CT 9 Features section - removed leaded device references. Ordering information - removed leaded devices. PDN CQ-13-02 expired. Updated datasheet format. 1/5/15

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