85310I-01 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Ten differential 2.5V, 3.3V LVPECL/ECL output pair
  • Two selectable differential input pairs
  • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 700MHz
  • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
  • Output skew: 30ps (typical)
  • Part-to-part skew: 140ps (typical)
  • Propagation delay: 2ns (typical)
  • Additive phase jitter, RMS: <0.13ps (typical)
  • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS compliant package 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 VCC CLK_SEL CLK0 nCLK0 nc CLK1 nCLK1 VEE nQ3 nQ4 nQ5 nQ6 VCCO nQ9 nQ8 nQ7 VCCO nQ0 nQ1 nQ2 VCCO VCCO Pin Assignment 85310I-01 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Block Diagram CLK0 nCLK0 nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 CLK1 nCLK1 CLK_SEL Pulldown Pullup Pulldown Pulldown Pullup

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Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V CC Power Positive supply pin. selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. 6 CLK1 Input Pulldown Non-inverting differential clock input. 7 nCLK1 Input Pullup Inverting differential clock input. 8V EE Power Negative supply pin. 9, 16, 25, 32 V CCO Power Output supply pins. 10, 11 nQ9, Q9 Output Diff erential output pair. LVPECL interface levels. 12, 13 nQ8, Q8 Output Diff erential output pair. LVPECL interface levels. 14, 15 nQ7, Q7 Output Diff erential output pair. LVPECL interface levels. 17, 18 nQ6, Q6 Output Diff erential output pair. LVPECL interface levels. 19, 20 nQ5, Q5 Output Diff erential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Diff erential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Diff erential output pair. LVPECL interface levels. 26, 27 nQ2, Q2 Output Diff erential output pair. LVPECL interface levels. 28, 29 nQ1, Q1 Output Diff erential output pair. LVPECL interface levels. 30, 31 nQ0, Q0 Output Diff erential output pair. LVPECL interface levels.

Rev I 7/8/15 3 LOW SKEW, 1-TO-10 DIFF ERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER 85310I-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Table 3B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Positive Supply Voltage 2.375 3.3 3.8 V VCCO Output Supply Voltage 2.375 3.3 3.8 V IEE Power Supply Current 120 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.3V 2 V CC + 0.3 V VCC = 2.5V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V IIH Input High Current CLK_SEL V CC = VIN = 3.8V 150 µA IIL Input Low Current CLK_SEL V CC = 3.8V, VIN = 0V -5 µA

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NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. NOTE 1: Outputs terminated with 50 to VCCO – 2V. Table 4. AC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. NOTE: All parameters measured at 500MHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65.

Rev I 7/8/15 5 LOW SKEW, 1-TO-10 DIFF ERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER 85310I-01 DATA SHEET Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter, RMS @ 155.52MHz = <0.13ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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Parameter Measurement Information LVPECL Output Load AC Test Circuit Part-to-Part Skew Propagation Delay Differential Input Level Output Skew Output Rise/Fall Time SCOPE Qx nQx VEE VCC, -0.375V to -1.8V VCCO tsk(pp) Part 1 Part 2 nQx Qx nQy Qy tPD nCLK[0:1] CLK[0:1] nQ[0:9] Q[0:9] V CMR Cross Points V PP VCC VEE nCLK[0:1] CLK[0:1] nQx Qx nQy Qy nQ[0:9] Q[0:9]

Rev I 7/8/15 7 LOW SKEW, 1-TO-10 DIFF ERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER 85310I-01 DATA SHEET Parameter Measurement Information Output Duty Cycle/Pulse Width/Period nQ[0:9] Q[0:9]

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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Application Information

Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 1. Single-Ended Signal Driving Differential Input additional protection, a 1k resistor can be tied from CLK to ground. should either be left floating or terminated.

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

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This section provides information on power dissipation and junction temperature for the ICS5310I-01. Equations and example calculations are also provided. The total power dissipation for the ICS5310I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 5 below. board (single layer or multi-layer). Table 5. Thermal Resistance JA for 32 Lead LQFP, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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Table 6. JA vs. Air Flow Table for a 32 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 7. Package Dimensions for 32 Lead LQFP

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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Ordering Information

Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" and “LN” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Rev I 7/8/15 17 LOW SKEW, 1-TO-10 DIFF ERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER 85310I-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B T4 4 AC Characteristics table - t PD row, revised value from 2.25ns Max. to 2.5ns Max. 4/29/02 B 8 Added Termination for LVPECL Outputs. 5/29/02 C T3D 4 Added LVPECL DC Characteristics table. Changed part number from ICS85310-01 to 85310I-01 in title and all subsequent areas throughout the datasheet. 7/26/02 D T3A 3 Power Supply table - increased max. value for IEE to 120mA from 30mA max. Power Considerations have re-adjusted to the increased IEE value. 10/22/02 E T2 2 Pin Characteristics - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - updated Outputs. Updated Single Ended Signal Driving Differential Input drawing and LVPECL Output Ter mination drawings. Added Differential Clock Input Interface section. Added Lead Free/Annealed part number. 6/14/04 F Features Section - added Additive Phase Jitter bullet. Added Additive Phase Jitter Section. Ordering Information Table - added Lead-Free Note. 6/22/05 F T8 Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number and marking. 1/16/06 G T3D 4 10 - 11 LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to Power Considerations - corrected power dissipation to reflect VOH max in Table 3D. 4/11/07 H T3B T3D LVCMOS DC Characteristics Table - corrected IIH/IIL specs. Added missing VIH/VIL 2.5V specs. LVPECL DC Characteristics Table - corrected VOH max. from 0.9V to VCCO - 0.9V. Updated Differential Clock Input Interface section. Added Termination for 2.5V LVPECL Outputs section. Converted datasheet format. 4/23/09 I Pin Assignment - corrected typo on pin 16 from “cco” to “Vcco”. Termination for 3.3V LVPECL Outputs - updated Diagrams 3A & 3B. Updated Header/Footer of datasheet. 1/15/10 Updated data sheet format. 7/8/15

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