85310I-11 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Ten differential 2.5V, 3.3V LVPECL/ECL output pair
  • Two selectable differential input pairs
  • Differential CLKx, nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 700MHz
  • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
  • Output skew: 30ps (typical)
  • Part-to-part skew: 140ps (typical)
  • Propagation delay: 2ns (typical)
  • Additive phase jitter, RMS: <0.13ps (typical)
  • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS compliant package Pin Assignment 85310I-11 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Block Diagram 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 VCC CLK_SEL CLK0 nCLK0 CLK_EN CLK1 nCLK1 VEE nQ3 nQ4 nQ5 nQ6 VCCO nQ9 nQ8 nQ7 VCCO nQ0 nQ1 nQ2 VCCO VCCO

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Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V CC Power Positive supply pin. selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input.

5 CLK_EN Input Pullup

Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. 6 CLK1 Input Pulldown Non-inverting differential clock input. 7 nCLK1 Input Pullup Inverting differential clock input. 8V EE Power Negative supply pin. 9, 16, 25, 32 V CCO Power Output supply pins. 10, 11 nQ9, Q9 Output Diff erential output pair. LVPECL interface levels. 12, 13 nQ8, Q8 Output Diff erential output pair. LVPECL interface levels. 14, 15 nQ7, Q7 Output Diff erential output pair. LVPECL interface levels. 17, 18 nQ6, Q6 Output Diff erential output pair. LVPECL interface levels. 19, 20 nQ5, Q5 Output Diff erential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Diff erential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Diff erential output pair. LVPECL interface levels. 26, 27 nQ2, Q2 Output Diff erential output pair. LVPECL interface levels. 28, 29 nQ1, Q1 Output Diff erential output pair. LVPECL interface levels. 30, 31 nQ0, Q0 Output Diff erential output pair. LVPECL interface levels.

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 input as described in Table 3B. Figure 1. CLK_EN Timing Diagram Wiring the Differential Input to Accept Single-ended Levels.

0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH

1 CLK1, nCLK1 Enabled Enabled

0 Biased; NOTE 1 LOW HIGH Single-ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-ended to Differential Non-Inverting

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Table 4C. DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Positive Supply Voltage 2.375 3.3 3.8 V VCCO Output Supply Voltage 2.375 3.3 3.8 V IEE Power Supply Current 120 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_EN V CC = VIN = 3.8V 5 µA CLK_SEL V CC = VIN = 3.8V 150 µA IIL Input Low Current CLK_EN V CC = 3.8V, VIN = 0V -150 µA CLK_SEL V CC = 3.8V, VIN = 0V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK[0:1], V CC = VIN = 3.8V 150 µA nCLK[0:1] V CC = VIN = 3.8V 5 µA IIL Input Low Current CLK[0:1] V CC = 3.8V, VIN = 0V -5 µA nCLK[0:1] V CC = 3.8V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Range; NOTE 1, 2 VEE + 0.5 V CC – 0.85 V

NOTE 1: Outputs terminated with 50 to VCCO – 2V. Table 5. AC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. NOTE: All parameters measured at 500MHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65.

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter, RMS @ 155.52MHz = <0.13ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)

Rev F 7/8/15 7 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER 85310I-11 DATA SHEET Parameter Measurement Information LVPECL Output Load AC Test Circuit Part-to-Part Skew Propagation Delay Differential Input Level Output Skew Output Rise/Fall Time SCOPE Qx nQx VEE VCC, -0.375V to -1.8V VCCO tsk(pp) Part 1 Part 2 nQx Qx nQy Qy tPD nCLK[0:1] CLK[0:1] nQ[0:9] Q[0:9] V CMR Cross Points V PP VCC VEE nCLK[0:1] CLK[0:1] nQx Qx nQy Qy nQ[0:9] Q[0:9]

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line impedance. For most 50 applications, R3 and R4 can be 100. guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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Recommendations for Unused Input Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS Control Pins The control pins have an internal pullup and pulldown; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

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This section provides information on power dissipation and junction temperature for the ICS5311I-01. Equations and example calculations are also provided. The total power dissipation for the ICS5311I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. board (single layer or multi-layer). Table 6. Thermal Resistance JA for 32 Lead LQFP, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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Table 7. JA vs. Air Flow Table for a 32 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 8. Package Dimensions for 32 Lead LQFP

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER

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Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Rev F 7/8/15 17 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER 85310I-11 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B T5 5 AC Characteristics table - t PD row, revised value from 2.25ns Max. to 2.5ns Max. 4/29/02 B 9 Added Termination for LVPECL Outputs. 5/29/02 C T4D 5 Added LVPECL DC Characteristics table. Changed part number from ICS85310-11 to 85310I-11 in title and all subsequent areas throughout the datasheet. 7/25/02 D T4A 4 Power Supply table - increased max. value for IEE to 120mA from 30mA max. Power Considerations have re-adjusted to the increased IEE value. 10/23/02 E Features Section - added Additive Phase Jitter bullet and Lead-Free bullet. Pin Characteristics - changed CIN 4pF max. to 4pF typical. AC Characteristics Table - added Additive Phase Jitter spec. Added Additive Phase Jitter Section. Added Termination for 2.5V LVPECL Outputs. Added Differential Clock Input Interface. Ordering Information Table - added Lead-Free Part Number and Note. 7/7/05 F T4D 5 11 - 12 LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to Power Considerations - corrected power dissipation to reflect VOH max in Table 4D. 4/11/07 F T4C Differential DC Characteristics Table -updated NOTES. AC Characteristics Table - added thermal note. Updated Wiring the Differential Input to Accept Single-ended Levels section. Updated Figure 4A & 4B. Ordering Information Table - corrected lead-free marking. Converted datasheet format. 6/9/10 Updated data sheet format. 7/8/15

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