8531-01 IDT | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 18

Technical content

Low Skew, 1-to-9, Differential-to- 3.3V LVPECL Fanout Buffer 8531-01 Data Sheet ©2016 Integrated Device Technology, Inc Revision F January 19, 20161 GENERAL DESCRIPTION The 8531-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The 8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew character- istics make the 8531-01 ideal for high performance work- station and server applications.

FEATURES

  • Nine differential 3.3V LVPECL outputs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
  • Maximum output frequency: 500MHz
  • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
  • Additive phase jitter, RMS: 0.17ps (typical)
  • Output skew: 50ps (maximum)
  • Part-to-part skew: 250ps (maximum)
  • Propagation delay: 2ns (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • Industrial Temperature information available upon request BLOCK DIAGRAM P IN ASSIGNMENT 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 2 CLK Input Pulldown Non-inverting differential clock input. 3 nCLK Input Pullup Inverting differential clock input. 4 CLK_SEL Input Pulldown Clock Select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 6 nPCLK Input Pullup Inverting differential LVPECL clock input.

8 CLK_EN Input Pullup

Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. 10, 11 nQ8, Q8 Output Differential output pair. LVPECL interface level. 12, 13 nQ7, Q7 Output Differential output pair. LVPECL interface level. 14, 15 nQ6, Q6 Output Differential output pair. LVPECL interface level. 18, 19 nQ5, Q5 Output Differential output pair. LVPECL interface level. 20, 21 nQ4, Q4 Output Differential output pair. LVPECL interface level. 22, 23 nQ3 Q3 Output Differential output pair. LVPECL interface level. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface level. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface level. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface level. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inverting

1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inverting

NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”. FIGURE 1. CLK_EN TIMING DIAGRAM

©2016 Integrated Device Technology, Inc Revision F January 19, 20164 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, TA = 0°C TO 70°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, TA = 0°C TO 70°C TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Power Supply Voltage 3.135 3.3 3.465 V V CCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 80 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH CLK_EN, CLK_SEL 2 3.765 V V IL CLK_EN, CLK_SEL -0.3 0.8 V I IH Input High Current CLK_EN V CC = V IN = 3.465V 5 µA CLK_SEL V CC = V IN = 3.465V 150 µA I IL Input Low Current CLK_EN V IN = 0V, V CC = 3.465V -150 µA CLK_SEL V IN = 0V, V CC = 3.465V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units I IH Input High Current CLK V CC = V IN = 3.465V 150 µA nCLK V CC = V IN = 3.465V 5 µA I IL Input Low Current CLK V IN = 0V, V CC = 3.465V -5 µA nCLK V IN = 0V, V CC = 3.465V -150 µA V PP Peak-to-Peak Input Voltage 0.15 1.3 V V CMR Common Mode Input Voltage; NOTE 1, 2 V EE + 0.5 V CC - 0.85 V NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is V CC + 0.3V. NOTE 2: Common mode input voltage is defi ned as V IH

TABLE 5. AC CHARACTERISTICS, V All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Driving only one input clock. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. at the differential cross points. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision F January 19, 20166 ADDITIVE PHASE JITTER The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels As with most timing specifi cations, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. of the device. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.17ps typical

©2016 Integrated Device Technology, Inc Revision F January 19, 20167 PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION DELAY

©2016 Integrated Device Technology, Inc Revision F January 19, 201611 The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recom- mended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock com- ponent process variations. TERMINATION FOR LVPECL OUTPUTS FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION

This section provides information on power dissipation and junction temperature for the 8531-01. Equations and example calculations are also provided. The total power dissipation for the 8531-01 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 80mA = 277.2mW
  • Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 30mW = 270mW Total Power _MAX (3.465V, with all outputs switching) = 277.2mW + 270mW = 547.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = Junction Temperature θ JA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.547W * 42.1°C/W = 93°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θ JA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 6. THERMAL RESISTANCE θ JA FOR 32-PIN LQFP FORCED CONVECTION

TABLE 7. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. PACKAGE DIMENSIONS

TABLE 9. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision F January 19, 201617 REVISION HISTORY SHEET Rev Table Page Description of Change Date B Separated LVCMOS rows into own table. Changed HSTL table to Differential table. Changed V PP value from 0.1 Min. to 0.15 Min.0Changed V CMR values from 0.13 Min, 1.3 Max. to 0.5 Min, V CC - 0.85. In LVPECL table, changed V CMR values from 0.7 Min, 2.5 Max. to 0.5 Min, V CC - 0.85. Changed V OH values from 1.9 Min., 2.3 Max. to V CC - 1.4 Min., V CC - 1.0 Max. Changed V OL values from 1.2 Min, 1.6 Max. to V CC - 2.0 Min, V CC - 1.7 Max. Changed V SWING values from 0.55 Min. to 0.6 Min. Changed tp LH & tp HL rows to t PD . Values stayed same. t R and t F values changed from 100 Min, 600 Max. to 300 Min., 700 Max. Changed t DC row to odc. Values stayed same. Deleted t S and t H rows. 6/15/01 Changed all V DDx to V CCx Changed V CCO to equal 3.3V ± 5% from 1.8V ± 0.2V. Updated Block Diagram. 6/18/01 B Changed V CMR value from 0.5 Min. to V EE + 0.5 Min. Changed V PP values from 0.15 Min, 1.3 Max, to 03. Min, 1 Max. Changed V CMR values from 0.5 Min., V CC - 0.85 Max. to V EE + 1.5 Min., V CC Max. 8/9/01 B 6, 7 Udated Figure 1, CLK_EN Timing Diagram. Updated Figure 2, Output Load Test Circuit. Revised labels on fi gures. 11/1/01 B 8 Added Termination for LVPECL Outputs section. 5/28/02 B Pin Description table - V CC description changed to “Core supply pin” from “Positive supply pin”. Power Supply Characteristics table - V CC description changed to “Core Supply Voltage” from “Positive Supply Voltage”. Output Load Test Circuit diagram - corrected V EE equation to read, V EE = -1.3V ± 0.165V from V EE = -1.3V ± 0.135V. 10/02/02 C T4A Pin Characteristics table - changed C IN 4pF max. to 4pF typical. Updated Absolute Maximum Ratings. Power Supply DC Characteristics table - changed I EE 70mA max. to 80mA max and deleted 50mA typical. Updated LVPECL Output Termination drawings. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Power Considerations - corrected Power Dissipation from 70mA to 80mA to corre- spond with I EE Updated format throughout the data sheet. 2/2/04 D T4D LVPECL DC Characteristics - changed VSWING max. limit from 850mV to 1.0V. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free note. 6/23/06 E T5 5 Features Section - added RMS Phase Jitter bullet. AC Characteristics Table - add RMS Phase Jitter spec. Added Additve Phase Jitter Plot. 12/4/06 F T4D 5 12 - 13 LVPECL DC Characteristics Table -corrected V OH max. from V CCO - 1.0V to V CCO - 0.9V. Power Considerations - corrected power dissipation to refl ect V OH max in Table 4D. 4/11/07 F T9 Removed ICS from the part number where needed. General Description - Removed ICS Chip and Hiperclocks. Features section - removed reference to leaded part. Ordering Information - removed quantity from tape and reel. Deleted LF note below the table. Updated header and footer. 1/19/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support