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Technical content

Features

  • Sixteen differential 3.3V LVPECL output pairs
  • CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input
  • Output skew: 75ps (maximum)
  • Additive phase jitter, RMS @ 106.25MHz: 0.162ps (typical)
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 13 14 15 16 17 18 19 20 21 22 23 24 VCCO Q11 nQ11 Q10 nQ10 VEE nQ9 nQ8 VCCO VCC CLK VCCO nQ0 nQ1 VEE nQ2 nQ3 VCCO VCC VCCO nQ7 nQ6 VEE nQ5 nQ4 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 VCCO nQ12 Q12 nQ13 Q13 VEE nQ14 Q14 nQ15 Q15 VCCO nCLK Pulldown Pullup Q15 nQ15 CLK0 nCLK0 Q14 Q13 Q12 nQ14 nQ13 nQ12 Q11 nQ11 Q10 nQ10 nQ9 nQ8 nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 Block Diagram Pin Assignment 8530I-01 48-Lead TQFP, E-Pad 7mm x 7mm x 1.0mm package body Y Package Top View 8530I-01 Datasheet Low Skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2, 3 Q11, nQ11 Output Differential output pair. LVPECL interface levels. 4, 5 Q10, nQ10 Output Differential output pair. LVPECL interface levels. 6, 19, 30, 43 V EE Power Negative power supply pins. 7, 8 Q9, nQ9 Output Differential output pair. LVPECL interface levels. 9, 10 Q8, nQ8 Output Differential output pair. LVPECL interface levels. 12, 13 V CC Power Positive power supply pins. 15, 16 Q7, nQ7 Output Differential output pair. LVPECL interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVPECL interface levels. 20, 21 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 22, 23 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 26, 27 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 28, 29 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 31, 32 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 33, 34 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 36 CLK Input Pulldown Non-inverting differential clock input. 37 nCLK Input Pullup Inverting differential clock input. 39, 40 Q15, nQ15 Output Differential output pair. LVPECL interface levels.

  1. 42 Q14, nQ14 Output Differential output pair. LVPECL interface levels.

44, 45 Q13, nQ13 Output Differential output pair. LVPECL interface levels. 46, 47 Q12, nQ12 Output Differential output pair. LVPECL interface levels.

Table 3. Clock Input Function Table NOTE 1: Refer to the Application Information section, Wiring the Differential Input to Accept single-ended Levels. NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability.

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 1: Outputs terminated with 50 to VCCO – 2V. Table 5. AC Electrical Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C been reached under these conditions. NOTE: All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

5©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015 8530I-01 Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter @ 106.25MHz 12kHz to 20MHz = 0.162ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)

6©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015 8530I-01 Datasheet Parameter Measurement Information LVPECL Output Load AC Test Circuit Output Skew Propagation Delay Differential Input Level Part-to-Part Skew Output Rise/Fall Time SCOPE Qx nQx VEE VCC, -1.3V ± -0.165V VCCO nQx Qx nQy Qy tPD Q[0:15] nQ[0:15] CLK nCLK nCLK CLK VCC VEE V CMR Cross Points V PP tsk(pp) Part 1 Part 2 nQx Qy Qx nQy Q[0:15] nQ[0:15]

7©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015 8530I-01 Datasheet Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Q[0:15] nQ[0:15]

and the inner edges of pad pattern for the leads to avoid any shorts. Enhance Leadframe Base Package, Amkor Technology. Figure 3. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

11©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015 8530I-01 Datasheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. Differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

This section provides information on power dissipation and junction temperature for the 8530I-01. Equations and example calculations are also provided. The total power dissipation for the 8530I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 34.1°C/W per Table 6 below. Table 6. Thermal Resistance JA for 48 Lead TQFP, Forced Convection

  1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 5. Figure 5. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 7. JA vs. Air Flow Table for a 48 Lead TQFP, E-Pad

Table 8. Package Dimensions 48 Lead TQFP, E-Pad

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

17©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015 8530I-01 Datasheet Revision History Sheet Rev Table Page Description of Change Date B1 6 Features Section - updated last bullet. Ordering Information Table - deleted leaded part rows. Updated datasheet header/footer. 12/1/15 A T9 Updated Wiring the Differential Input to Accept Singe-ended Levels application note. Ordering Information Table - deleted “Lead-Free” in Package column for non-LF parts. Corrected lead-free Shipping Packaging information. Updated header/footer to new format. 2/22/11

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