8530FY-01LF

ICS8530-01 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: mamiller
• PDF pages: 18

Technical content

Features

• Sixteen differential 3.3V LVPECL outputs
• CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input
• Output skew: 75ps (maximum)
• Part-to-part skew: 305ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• Full 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 13 14 15 16 17 18 19 20 21 22 23 24 VCCO Q11 nQ11 Q10 nQ10 VEE nQ9 nQ8 VCCO VCC CLK VCCO nQ0 nQ1 VEE nQ2 nQ3 VCCO VCC VCCO nQ7 nQ6 VEE nQ5 nQ4 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 VCCO nQ12 Q12 nQ13 Q13 VEE nQ14 Q14 nQ15 Q15 VCCO nCLKPulldown Pullup Q15 nQ15 CLK nCLK Q14 Q13 Q12 nQ14 nQ13 nQ12 Q11 nQ11 Q10 nQ10 nQ9 nQ8 nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 Block Diagram Pin Assignment ICS8530-01 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2, 3 Q11, nQ11 Output Differential output pair. LVPECL interface levels. 4, 5 Q10, nQ10 Output Differential output pair. LVPECL interface levels. 6, 19, 30, 43 V EE Power Negative supply pins. 7, 8 Q9, nQ9 Output Differential output pair. LVPECL interface levels. 9, 10 Q8, nQ8 Output Differential output pair. LVPECL interface levels. 12, 13 V CC Power Power supply pins. 15, 16 Q7, nQ7 Output Differential output pair. LVPECL interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVPECL interface levels. 20, 21 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 22, 23 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 26, 27 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 28, 29 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 31, 32 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 33, 34 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 36 CLK Input Pulldown Non-inverting differential clock input. 37 nCLK Input Pullup Inverting differential clock input. 39, 40 Q15, nQ15 Output Differential output pair. LVPECL interface levels. 41, 42 Q14, nQ14 Output Differential output pair. LVPECL interface levels. 44, 45 Q13, nQ13 Output Differential output pair. LVPECL interface levels. 46, 47 Q12, nQ12 Output Differential output pair. LVPECL interface levels.

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 3 ©2012 Integrated Device Technology, Inc. Table 3. Clock Input Function Table NOTE 1: Refer to the Application Information section, Wiring the Differential Input to Accept single-ended Levels. NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability.

0 Biased; NOTE 1 LOW HIGH Single-E nded to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 4 ©2012 Integrated Device Technology, Inc. NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 1: Outputs terminated with 50 to VCCO – 2V. Table 5. AC Electrical Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C been reached under these conditions. NOTE All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 5 ©2012 Integrated Device Technology, Inc. ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter @ 106.25MHz 12kHz to 20MHz = 0.03ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 6 ©2012 Integrated Device Technology, Inc. ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Parameter Measurement Information 3.3V Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period Differential Input Level Part-to-Part Skew Propagation Delay SCOPE Qx nQx VEE -1.3V±0.165V VCC, VCCO nQx Qx nQy Qy t sk(o) tPW tPERIOD tPW tPERIOD odc = x 100% Q[0:15] nQ[0:15] nCLK CLK VCC VEE VCMR Cross Points V PP t sk(pp) Part 1 Part 2 nQx Qy Qx nQy tPD Q[0:15] nQ[0:15] CLK nCLK

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 7 ©2012 Integrated Device Technology, Inc. ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Parameter Measurement Information, continued Output Rise/Fall Time Applications Information Recommendations for Unused Output Pins Outputs: LVPECL Outputs The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 20% 80% 80% 20% tR tF VSWING Q[0:15] nQ[0:15]

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 10 ©2012 Integrated Device Technology, Inc. ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 11 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8530-01. Equations and example calculations are also provided. The total power dissipation for the ICS8530-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 146mA = 505.89mW
• Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 16 * 30mW = 480mW Total Power_MAX (3.465V, with all outputs switching) = 505.89mW + 480mW = 985.89mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 53.9°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 6. Thermal Resistance JA for 48 Lead LQFP, Forced Convection

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 12 ©2012 Integrated Device Technology, Inc.

1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination

• For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V
• For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCOC_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW VOUT VCCO VCCO - 2V RL 50Ω

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 13 ©2012 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 48 Lead LQFP

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 14 ©2012 Integrated Device Technology, Inc. Table 8. Package Dimensions for 48 Lead LQFP

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 15 ©2012 Integrated Device Technology, Inc. Table 9. Ordering Information NOTE: "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS8530FY-01 REVISION G NOVEMBER 15, 2012 16 ©2012 Integrated Device Technology, Inc. ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change Date B 5-6 Updated figures. Added Termination for LVPECL Outputs section. 05/28/02 B Pin Description table - VCC description changed to "Core supply pin" from "Positive supply pin". Output Load Test Circuit diagram - corrected VEE equation to read, 10/02/02 C T4A Pin Characteristics table - changed C IN 4pF max. to 4pF typical. Updated AMR Output rating. Power Supply table - changed I EE max. from 120mA to 140mA. Updated Single Ended Signal Driving Differential Input diagram. Added Differential Clock Input Interface section. Power Considerations, changed IEE to 140mA to reflect the Power Supply table and recalculated the equations. Update format throughout the data sheet. 4/7/04 C T9 12 Added "Lead-Free" marking to Ordering Information Table. 6/29/04 D Features section - added Additive Phase Jitter bullet. AC Characteristics table - added tjit row. Added Additive Phase Jitter section. 2/28/05 E T4C LVPECL DC Characteristics - changed V SWING (max) limit from 850mV to 1.0V. Corrected VOH (max) limit from VCCO - 1.0V to VCCO - 0.9V. Added Recommendations for Unused Output Pins. Ordering Information Table - added lead-free note. 5/19/06 F T4A T4B Pin Description Table - change V CC description from “Core” to “Power”. Pin Characteristics Table - change CIN from 4pF typical to 3pF typical. Absolute Maximum Rating - updated Thermal Impedance. Power Supply DC Characteristics Table - change IEE from 140mA max to 146mA max. Differential DC Characteristics Table - updated notes. AC Characteristics Table - changed part-to-part skew spec and Output Rise/Fall Time spec. Updated Wiring the Differential Input to Accept Single-ended Levels. Updated Differential Clock Input Interface. Updated Figures 3A and 3B. Updated Power Considerations to reflect power supply table, and updated Thermal Resistance Table. Updated Thermal Table and Transistor Count. Ordering Information Table - deleted “ICS” prefix in Part/Order column. Changed revision from “D” to “F”. Converted datasheet format. 11/18/10 G T5 4 AC Characteristics Table - corrected typical pa rt-to-part skew spec from 150 to 148ps. 11/30/10 G T9 15 Removed leaded orderable parts from Ordering Information table 11/15/12

ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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