8530 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Sixteen differential LVPECL output pairs
  • CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 2.5V LVPECL levels with a resistor bias on nCLK input
  • Output skew: 50ps (maximum)
  • Part-to-part skew: 250ps (maximum)
  • Propagation delay: 2ns (maximum)
  • 3.3V core, 2.5V output operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 13 14 15 16 17 18 19 20 21 22 23 24 VCCO Q11 nQ11 Q10 nQ10 VEE nQ9 nQ8 VCCO VCC CLK VCCO nQ0 nQ1 VEE nQ2 nQ3 VCCO VCC VCCO nQ7 nQ6 VEE nQ5 nQ4 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 VCCO nQ12 Q12 nQ13 Q13 VEE nQ14 Q14 nQ15 Q15 VCCO nCLK Pulldown Pullup Q15 nQ15 CLK nCLK Q14 Q13 Q12 nQ14 nQ13 nQ12 Q11 nQ11 Q10 nQ10 nQ9 nQ8 nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 Block Diagram Pin Assignment 8530 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View

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8530 DATA SHEET

Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2, 3 Q11, nQ11 Output Differential output pair. LVPECL interface levels. 4, 5 Q10, nQ10 Output Differential output pair. LVPECL interface levels. 6, 19, 30, 43 V EE Power Negative power supply pins. 7, 8 Q9, nQ9 Output Differential output pair. LVPECL interface levels. 9, 10 Q8, nQ8 Output Differential output pair. LVPECL interface levels. 12, 13 V CC Power Positive power supply pins. 15, 16 Q7, nQ7 Output Differential output pair. LVPECL interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVPECL interface levels. 20, 21 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 22, 23 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 26, 27 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 28, 29 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 31, 32 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 33, 34 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 36 CLK Input Pulldown Non-inverting differential clock input. 37 nCLK Input Pullup Inverting differential clock input. 39, 40 Q15, nQ15 Output Differential output pair. LVPECL interface levels.

  1. 42 Q14, nQ14 Output Differential output pair. LVPECL interface levels.

44, 45 Q13, nQ13 Output Differential output pair. LVPECL interface levels. 46, 47 Q12, nQ12 Output Differential output pair. LVPECL interface levels.

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Table 3. Clock Input Function Table Wiring the Differential Input to Accept single-ended Levels. Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability.

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

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NOTE 1: Common mode input voltage is defined as VIH. NOTE 1: Outputs terminated with 50 to VCCO – 2V. Table 5. AC Electrical Characteristics, VCC = 3.3V ± 5%, VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C been reached under these conditions. NOTE All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER

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Parameter Measurement Information 3.3V Core/ 2.5V LVPECL Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period Differential Input Level Part-to-Part Skew Propagation Delay SCOPE Qx nQx LVPECL VEE -0.5V±0.125V VCC VCCO 2.8V±0.04V nQx Qx nQy Qy Q[0:15] nQ[0:15] nCLK CLK VCC VEE VCMR Cross Points VPP tsk(pp) Part 1 Part 2 nQx Qy Qx nQy tPD Q[0:15] nQ[0:15] CLK nCLK

LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER

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Parameter Measurement Information, continued Output Rise/Fall Time Applications Information Recommendations for Unused Output Pins Outputs: LVPECL Outputs The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Q[0:15] nQ[0:15]

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line impedance. For most 50 applications, R3 and R4 can be 100. guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

REVISION G 06/26/15 8 LOW SKEW, 1-TO 16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for IDT LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. Figure 2A. CLK/nCLK Input Driven by an IDT LVHSTL Driver Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2F. CLK/nCLK Input Dri ven by a 2.5V SSTL Driver 50Ω 50Ω 1.8V Zo = 50Ω Zo = 50Ω CLK nCLK 3.3V LVHSTL IDT LVHSTL Driver Differential Input HCSL *R3 *R4 CLK nCLK 3.3V 3.3V Differential Input CLK nCLK Differential Input SSTL 2.5V Zo = 60Ω Zo = 60Ω 2.5V 3.3V 120Ω 120Ω 120Ω 120Ω

LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER

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Termination for 2.5V LVPECL Outputs Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. Figure 3A. 2.5V LVPECL Driver Termination Example Figure 3C. 2.5V LVPECL Driver Termination Example Figure 3B. 2.5V LVPECL Driver Termination Example 2.5V LVPECL Driver VCC = 2.5V 2.5V 2.5V 50Ω 50Ω 250 Ω 250 Ω 62.5 Ω 62.5 Ω 2.5V LVPECL Driver VCC = 2.5V 2.5V 50Ω 50Ω Ω Ω 2.5V LVPECL Driver VCC = 2.5V 2.5V 50Ω 50Ω Ω Ω Ω

This section provides information on power dissipation and junction temperature for the 8530. Equations and example calculations are also provided. The total power dissipation for the 8530 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 47.9°C/W per Table 6 below. Table 6. Thermal Resistance JA for 48 Lead LQFP, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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  1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. Figure 4. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 7. JA vs. Air Flow Table for a 48 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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Table 8. Package Dimensions for 48 Lead LQFP

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Table 10. Pin 1 Orientation in Tape and Reel Packaging

8 Quadrant 1 (EIA-481-C)

LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER

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Rev Table Page Description of Change Date C 5-6 Updated figures. Added Termination for LVPECL Outputs section. 5/28/02 C 5 Output Load Test Circuit - corrected VEE equation to read: D T4C 8-9 Pin Characteristics - changed CIN 4pF max. to 4pF typical. LVPECL Characteristics - changed VOH from VCCO - 1.4V min. to VCCO - 1.1V min. Changed VCCO - 1.0V max. to VCCO - 0.7V max. Changed VOL from VCCO - 1.7V max. to VCCO - 1.4V max. Output Load Test Circuit - corrected VEE equation to read: Corrected VCC equation to read ""VCC = 2.8V ± 0.04V"" from ""VCC = 2.8V"". Updated Figure 1, Single Ended Signal Driving Differential Input diagram. Updated Figures 2A and 2B, LVPECL Output Termination diagrams. Added Differential Clock Input Interface section. Adjusted worse case power dissipation to reflect VOH/VOL. Updated format throughout datasheet. 11/20/03 E T4A 3 Power Supply Table - changed I EE max. from 115mA to 125mA. 12/2/03 E T4B Differential DC Characteristics Table - updated notes. Added Recommendations for Unused Output Pins section. Updated Wiring the Differential Input to Accept Single-ended Levels section. Updated Termination for LVPECL Outputs section. Ordering Information Table - deleted “ICS” prefix from part/order column. Added lead-free marking. Converted datasheet format. 9/15/10 F T4A 3 Power Supply DC Characteristics Table - changed IEE spec to 150mA maximum. Power Considerations, updated calculations to coincide with new IEE spec. 10/11/11 G T10 14 Added Pin 1 Orientation in Tape and Reel Packaging Table. 6/26/15

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licen ses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary envi ronmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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