85304AGI-01LF | DigiCamel IC Datasheet

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ICS85304I-01 IDT | Alldatasheet

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PDF pages: 15

Technical content

Features

Five 3.3V differential LVPECL output pairs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx input pairs can accept the following differential levels: LVDS, LVPECL, LVHSTL and HCSL levels
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx inputs
Output skew: 60ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 2.1ns (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) package Block Diagram Pin Assignment ICS85304I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View D Q LE nQ0 nQ1 nQ2 nQ3 nQ4 CLK_EN CLK0 nCLK0 CLK_SEL Pulldown Pullup Pullup Pulldown CLK1 nCLK1 Pullup Pulldown nQ3 nQ2 nQ1 nQ0 nQ4 VCC CLK_EN VCC nCLK1 CLK1 VEE nCLK0 CLK0 CLK_SEL VCC

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 2 ©2013 Integrated Device Technology, Inc. Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 Q0, nQ0 Output Differential ou tput pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential ou tput pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential ou tput pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential ou tput pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential ou tput pair. LVPECL interface levels. 11, 18, 20 V CC Power Positive supply pins. selects CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels. 13 CLK0 Input Pulldown Non-inverting differential clock input. 14 nCLK0 Input Pullup Inverting differential clock input. 15 V EE Power Negative supply pin. 16 CLK1 Input Pulldown Non-inverting differential clock input. 17 nCLK1 Input Pullup Inverting differential clock input.

19 CLK_EN Input Pullup

Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL/LVCMOS interface levels.

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 3 ©2013 Integrated Device Technology, Inc. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B. Figure 1. CLK_EN Timing Diagram Wiring the Differential Input to Accept Single-Ended Levels.

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 4 ©2013 Integrated Device Technology, Inc. ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. Differential DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 91.1°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 55 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_EN V CC = VIN = 3.465V 5 µA CLK_SEL V CC = VIN = 3.465V 150 µA IIL Input Low Current CLK_EN V CC = 3.465V, VIN = 0V -150 µA CLK_SEL V CC = 3.465V, VIN = 0V -5 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current nCLK0, nCLK1 V CC = VIN = 3.465V 5 µA CLK0, CLK1 V CC = VIN = 3.465V 150 µA IIL Input Low Current nCLK0, nCLK1 V CC = 3.465V, VIN = 0V -150 µA CLK0, CLK1 V CC = 3.465V, VIN = 0V -5 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 V CC – 0.85 V

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 5 ©2013 Integrated Device Technology, Inc. NOTE 1: Outputs terminated with 50 to VCC – 2V. Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C individually under normal operating conditions and not valid simultaneously. NOTE 1: Measured from the differential input crossing point to the differential output crosspoint. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 6 ©2013 Integrated Device Technology, Inc. ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER Parameter Measurement Information 3.3V Output Load AC Test Circuit Output Skew Propagation Delay Differential Input Level Part-to-Part Skew Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC 2V% 1.3V ± 0.165V tsk(o) nQx Qx nQy Qy tPD nQ[0:4] Q[0:4] CLK0, CLK1 nCLK0, nCLK1 VCC VEE nCLK0, nCLK1 CLK0, CLK1 VCMR Cross Points V PP tsk(pp) Part 1 Part 2 nQx Qx nQy Qy nQ[0:4] Q[0:4] tPW tPERIOD tPW tPERIOD odc = x 100%

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 7 ©2013 Integrated Device Technology, Inc. ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER Parameter Measurement Information, continued Output Rise/Fall Time 20% 80% 80% 20% tR tF VSWING nQ[0:4] Q[0:4]

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 10 ©2013 Integrated Device Technology, Inc. ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. Outputs: LVPECL Outputs All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 11 ©2013 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS85304I-01. Equations and example calculations are also provided. The total power dissipation for the ICS85304I-01 is the sum of the core power plus the power dissipated due to the load. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated due to the load. maximum recommended junction temperature for HiPerClockS devices is 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below. Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection

Ordering Information

Table 9. Ordering Information

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2013. All rights reserved.

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Product Information

85304AGI-01LF specifications and overview.

Summary

Low Skew, 1-to-5, Differential-To-3.3V LVPECL Fanout Buffer

Description

Low Skew, 1-to-5, Differential-To-3.3V LVPECL Fanout Buffer

Source title 85304AGI-01LF Datasheet(PDF) - Integrated Device Technology

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