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Technical content
Features
- Five 3.3V differential LVPECL output pairs
- Selectable differential CLKx, nCLKx input pairs
- CLKx, nCLKx input pairs can accept the following differential levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels
- Maximum output frequency: 650MHz
- Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx inputs
- Output skew: 35ps (maximum)
- Part-to-part skew: 150ps (maximum)
- Propagation delay: 2.1ns (maximum)
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature D Q LE nQ0 nQ1 nQ2 nQ3 nQ4 CLK_EN CLK0 nCLK0 CLK_SEL Pulldown Pullup Pullup Pulldown CLK1 nCLK1 Pullup Pulldown nQ3 nQ2 nQ1 nQ0 nQ4 VCC CLK_EN VCC nCLK1 CLK1 VEE nCLK0 CLK0 CLK_SEL VCC Pin Assignment ICS85304-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Block Diagram
ICS843N001BGI REVISION E DECEMBER 19, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11, 18, 20 V CC Power Power supply pins. CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels. 13 CLK0 Input Pulldown Non-inverting differential clock input. 14 nCLK0 Input Pullup Inverting differential clock input. EE Power Negative supply pin. 16 CLK1 Input Pulldown Non-inverting differential clock input. 17 nCLK1 Input Pullup Inverting differential clock input.
19 CLK_EN Input Pullup
LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL/LVCMOS interface levels.
ICS843N001BGI REVISION E DECEMBER 19, 2012 3 ©2012 Integrated Device Technology, Inc. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B. Figure 1. CLK_EN Timing Diagram NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting
1 Biased; NOTE 1 HIGH LOW Single-E nded to Differential Non-Inverting
ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER ICS843N001BGI REVISION E DECEMBER 19, 2012 4 ©2012 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Table 4C. Differential DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 55 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 3.765 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_EN V CC = VIN = 3.465V 5 µA CLK_SEL V CC = VIN = 3.465V 150 µA IIL Input Low Current CLK_EN V CC = 3.465V, VIN = 0V -150 µA CLK_SEL V CC = 3.465V, VIN = 0V -5 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current nCLK0, nCLK1 V CC = VIN = 3.465V 5 µA CLK0, CLK1 V CC = VIN = 3.465V 150 µA IIL Input Low Current nCLK0, nCLK1 V CC = 3.465V, VIN = 0V -150 µA CLK0, CLK1 V CC = 3.465V, VIN = 0V -5 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 V EE + 0.5 V CC – 0.85 V
ICS843N001BGI REVISION E DECEMBER 19, 2012 5 ©2012 Integrated Device Technology, Inc. NOTE 1: Outputs terminated with 50 to VCC – 2V. Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C has been reached under these conditions. NOTE: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER ICS843N001BGI REVISION E DECEMBER 19, 2012 6 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V Output Load Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time Differential Input Level Part-to-Part Skew Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC 1.3V ± 0.165V- tsk(o) nQx Qx nQy Qy tPD nQ[0:4] Q[0:4] nCLK0, CLK0, nCLK1 CLK1 20% 80% 80% 20% tR tF VSWING nQ[0:4] Q[0:4] VCC VEE nCLK0, nCLK1 CLK0, CLK1 VCMR Cross Points VPP tsk(pp) Part 1 Part 2 nQx Qx nQy Qy nQ[0:4] Q[0:4] tPW tPERIOD tPW tPERIOD odc = x 100%
ICS843N001BGI REVISION E DECEMBER 19, 2012 9 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullup or pulldown; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. Outputs: LVPECL Outputs All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Fi gure 3B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V
ICS843N001BGI REVISION E DECEMBER 19, 2012 10 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS85304-01. Equations and example calculations are also provided. The total power dissipation for the ICS85304-01 is the sum of the core power plus the output power dissipated due to loading. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating output power dissipated due to loading. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below. Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS843N001BGI REVISION E DECEMBER 19, 2012 11 ©2012 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
ICS843N001BGI REVISION E DECEMBER 19, 2012 12 ©2012 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS843N001BGI REVISION E DECEMBER 19, 2012 13 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER ICS843N001BGI REVISION E DECEMBER 19, 2012 14 ©2012 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date A T4B T4D Replaced tpLH and tpHL with tPD at the same values. Replaced tPW and values of tCYCLE/2 - 40 min., tCYCLE/2 typ., tCYCLE/2 + 40 max. with odc at values of 48% min., 50% typ., 52% max. 5/14/01 B T4D 5 LVPECL DC Characteristics Table - added I IH, IIL, VPP, and VCMR rows. AC Characteristics Table - tR and tF values changed from 275ps min to 300ps min; 650ps max. to 700ps max. 5/22/01 C T4D 5 Differential DC Characteristics Table - V CMR values changed from VCC - 0.85V max. to VCC. 8/21/01 C 3 Revised Figure 1, CLK_EN Timing Diagram. 10/17/01 C 3 Revised Figure 1, CLK_EN Timing Diagram. 11/2/01 C T3B 3 Revised Inputs heading from CLK or CLK, nPCLK or nPCLK to CLK or PCLK, nCLK or nPCLK. 12/28/01 C 8 Added Termination for LVEPCL Output section. 5/30/02 C 3.3V Output Load Test Circuit Diagram - corrected VEE = -1.3V ± 0.135V to Updated Output Rise/Fall Time Diagram. 8/26/02 D Added Lead-Free bullet in Features section. Pin Characteristics table - changed C IN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Outputs rating. Updated Parameter Measurement Information. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Ordering Information table - added Lead Free part number. 6/17/04 E Per Document Errata, NEN-08-03, corrected name of PCLK/nPCLK to CLK1/nCLK1 and changed CLK/nCLK to CLK0/nCLK0 throughout the datasheet. Updated Differential Clock Input Interface section. Deleted LVPECL Clock Input Interface section. Added Recommendations for Unused Input and Output Pins section. Power Considerations - corrected Junction Temperature calculations. Ordering Information Table - corrected marking. Updated format throughout the datasheet. 6/20/08 E 3 Corrected Figure 1, CLK_EN Timing Diagram. 7/8/08 E T4[A:D] 4 - 5 Features section - deleted package information DC Characteristic Tables - corrected table heading temperature from -40C to 85C to 0C to 70C. AC Characteristic Table - corrected table heading temperature from -40C to 85C to 0C to 70C. Added general note to table. Updated Wiring the Differential Input to Accept Single-ended Levels application note. Ordering Information Table - deleted non lead-free parts. Deleted Tape & Reel quantity from Shipping Packaging column. 12/19/12
ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DI FFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.
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