85304-01 IDT | Alldatasheet
Document overview
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Technical content
Features
- Five 3.3V differential LVPECL output pairs
- Selectable differential CLKx, nCLKx input pairs
- CLKx, nCLKx input pairs can accept the following differential levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels
- Maximum output frequency: 650MHz
- Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx inputs
- Output skew: 35ps (maximum)
- Part-to-part skew: 150ps (maximum)
- Propagation delay: 2.1ns (maximum)
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature Block Diagram Pin Assignment 85304-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View D Q LE nQ0 nQ1 nQ2 nQ3 nQ4 CLK_EN CLK0 nCLK0 CLK_SEL Pulldown Pullup Pullup Pulldown CLK1 nCLK1 Pullup Pulldown nQ3 nQ2 nQ1 nQ0 nQ4 VCC CLK_EN VCC nCLK1 CLK1 VEE nCLK0 CLK0 CLK_SEL VCC Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer 85304-01 Data Sheet
Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 Q0, nQ0 Output Differential ou tput pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential ou tput pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential ou tput pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential ou tput pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential ou tput pair. LVPECL interface levels. 11, 18, 20 V CC Power Power supply pins. selects CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels. 13 CLK0 Input Pulldown Non-inverting differential clock input. 14 nCLK0 Input Pullup Inverting differential clock input. 15 V EE Power Negative supply pin. 16 CLK1 Input Pulldown Non-inverting differential clock input. 17 nCLK1 Input Pullup Inverting differential clock input.
19 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL/LVCMOS interface levels.
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B. Figure 1. CLK_EN Timing Diagram Wiring the Differential Input to Accept Single-Ended Levels.
0 Biased; NOTE 1 LOW HIGH Single-Ended to
1 Biased; NOTE 1 HIGH LOW Single-Ended to
4©2015 Integrated Device Technology, Inc Revision E December 2, 2015 85304-01 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Table 4C. Differential DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 55 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 3.765 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_EN V CC = VIN = 3.465V 5 µA CLK_SEL V CC = VIN = 3.465V 150 µA IIL Input Low Current CLK_EN V CC = 3.465V, VIN = 0V -150 µA CLK_SEL V CC = 3.465V, VIN = 0V -5 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current nCLK0, nCLK1 V CC = VIN = 3.465V 5 µA CLK0, CLK1 V CC = VIN = 3.465V 150 µA IIL Input Low Current nCLK0, nCLK1 V CC = 3.465V, VIN = 0V -150 µA CLK0, CLK1 V CC = 3.465V, VIN = 0V -5 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 V CC – 0.85 V
NOTE 1: Outputs terminated with 50 to VCC – 2V. Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C has been reached under these conditions. NOTE: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
6©2015 Integrated Device Technology, Inc Revision E December 2, 2015 85304-01 Data Sheet Parameter Measurement Information 3.3V Output Load Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time Differential Input Level Part-to-Part Skew Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC -1.3V ± 0.165V nQx Qx nQy Qy tPD nQ[0:4] Q[0:4] nCLK0, CLK0, nCLK1 CLK1 nQ[0:4] Q[0:4] VCC VEE nCLK0, nCLK1 CLK0, CLK1 V CMR Cross Points V PP tsk(pp) Part 1 Part 2 nQx Qx nQy Qy nQ[0:4] Q[0:4]
9©2015 Integrated Device Technology, Inc Revision E December 2, 2015 85304-01 Data Sheet Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullup or pulldown; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. Outputs: LVPECL Outputs All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
This section provides information on power dissipation and junction temperature for the 85304-01. Equations and example calculations are also provided. The total power dissipation for the 85304-01 is the sum of the core power plus the output power dissipated due to loading. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating output power dissipated due to loading. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below. Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
13©2015 Integrated Device Technology, Inc Revision E December 2, 2015 85304-01 Data Sheet
Ordering Information
Table 9. Ordering Information
14©2015 Integrated Device Technology, Inc Revision E December 2, 2015 85304-01 Data Sheet Revision History Sheet Rev Table Page Description of Change Date A T4B T4D Replaced tpLH and tpHL with tPD at the same values. Replaced tPW and values of tCYCLE/2 - 40 min., tCYCLE/2 typ., tCYCLE/2 + 40 max. with odc at values of 48% min., 50% typ., 52% max. 5/14/01 B T4D 5 LVPECL DC Characteristics Table - added I IH, IIL, VPP, and VCMR rows. AC Characteristics Table - tR and tF values changed from 275ps min to 300ps min; 650ps max. to 700ps max. 5/22/01 C T4D 5 Differential DC Characteristics Table - V CMR values changed from VCC - 0.85V max. to VCC. 8/21/01 C 3 Revised Figure 1, CLK_EN Timing Diagram. 10/17/01 C 3 Revised Figure 1, CLK_EN Timing Diagram. 11/2/01 C T3B 3 Revised Inputs heading from CLK or CLK, nPCLK or nPCLK to CLK or PCLK, nCLK or nPCLK. 12/28/01 C 8 Added Termination for LVEPCL Output section. 5/30/02 C 3.3V Output Load Test Circuit Diagram - corrected VEE = -1.3V ± 0.135V to Updated Output Rise/Fall Time Diagram. 8/26/02 D Added Lead-Free bullet in Features section. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Outputs rating. Updated Parameter Measurement Information. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Ordering Information table - added Lead Free part number. 6/17/04 E Per Document Errata, NEN-08-03, corrected name of PCLK/nPCLK to CLK1/nCLK1 and changed CLK/nCLK to CLK0/nCLK0 throughout the datasheet. Updated Differential Clock Input Interface section. Deleted LVPECL Clock Input Interface section. Added Recommendations for Unused Input and Output Pins section. Power Considerations - corrected Junction Temperature calculations. Ordering Information Table - corrected marking. Updated format throughout the datasheet. 6/20/08 E 3 Corrected Figure 1, CLK_EN Timing Diagram. 7/8/08 E T4[A:D] 4 - 5 Features section - deleted package information DC Characteristic Tables - corrected table heading temperature from -40C to 85C to 0C to 70C. AC Characteristic Table - corrected table heading temperature from -40C to 85C to 0C to 70C. Added general note to table. Updated Wiring the Differential Input to Accept Single-ended Levels application note. Ordering Information Table - deleted non lead-free parts. Deleted Tape & Reel quantity from Shipping Packaging column. 12/19/12 E Updated Header and Footer format. 12/2/15
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