852911I

852911I RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
• PDF pages: 17

Technical content

Low Skew, 1-to-9 Differential-to-HSTL Fanout Buffer 852911I Data Sheet ©2016 Integrated Device Technology, Inc Revision A January 21, 20161 ICS852911I 25 24 23 22 21 20 19 GND CLK_SEL HSTL_CLK V DD nHSTL_CLK PECL_CLK nPECL_CLK nQ8 nQ7 VDDO nQ6 Q6 nQ2 nQ1 VDDO nQ0 nQ3 V DDO nQ4 nQ5 5 6 7 8 9 10 11 GENERAL DESCRIPTION The 852911I is a low skew, 1-to-9 Differential-to-HSTL Fanout Buffer. The 852911I has two selectable clock inputs which can accept most differential input levels. Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the 852911I ideal for today’s most advanced applications, such as IA64 and static RAMs.

FEATURES

• 9 HSTL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• HSTL_CLK, nHSTL_CLK pa ir can accept the following dif- ferential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• PECL_CLK, nPECL_CLK supports the follow ing input types: LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Output skew: 100ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 1.7ns (maximum)
• VOH = 1.4V (maximum)
• 3.3V core, 1.6V to 3.6V output supply range
• -40°C to 85°C ambient operating temperature BLOCK DIAGRAM P IN ASSIGNMENT HSTL_CLK nHSTL_CLK PECL_CLK nPECL_CLK nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 CLK_SEL 28-Lead PLCC 11.6mm x 11.4mm x 4.1mm package body V Package Top View

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. CONTROL INPUT FUNCTION TABLE

0 HSTL_CLK, nHSTL_CLK

1 PECL_CLK, nPECL_CLK

1V DD Power Core supply p in. Pulldown Inverting differential clock input. VCC/2 default when left fl oating. 3 PECL_CLK Input Pulldown Non- inverting differential LVPECL clock input. Pulldown Inverting differential clock input. VCC/2 default when left fl oating. 5, 6 nQ8, Q8 Output D ifferential output pair. HSTL interface level. 7, 9 nQ7, Q7 Output D ifferential output pair. HSTL interface level. 8, 15, 22 V DDO Power Output supply p ins. 10, 11 nQ6, Q6 Output D ifferential output pair. HSTL interface level. 12, 13 nQ5, Q5 Output D ifferential output pair. HSTL interface level. 14, 16 nQ4, Q4 Output D ifferential output pair. HSTL interface level. 17, 18 nQ3 Q3 Output D ifferential output pair. HSTL interface level. 19, 20 nQ2, Q2 Output D ifferential output pair. HSTL interface level. 21, 23 nQ1, Q1 Output D ifferential output pair. HSTL interface level. 24, 25 nQ0, Q0 Output D ifferential output pair. HSTL interface level. 26 GND Power Power supply ground .

27 CLK_SEL Input Pulldown

Clock select input. When HIGH, selects PECL_CLK, nPECL_CLK inputs. When LOW, selects HSTL_CLK, nHSTL_CLK. LVTTL / LVCMOS interface levels. 28 HSTL_CLK Input Pulldown Non- inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

©2016 Integrated Device Technology, Inc Revision A January 21, 20163 Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3 .03 .33 .6V VDDO Output Supply Voltage 1 .63 .33 .6V IDD Power Supply Current 95m A Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH CLK_SEL 2 V DD + 0.3V VIL CLK_SEL -0 .30 .8V IIH Input High Current CLK_SEL V IN = VDD = 3.6V 150 µA IIL Input Low Current CLK_SEL V IN = 0V, VDD = 3.6V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PECL_CLK V DD = VIN = 3.6V 150 µA nPECL_CLK V DD = VIN = 3.6V 150 µA IIL Input Low Current PECL_CLK V DD = 3.6V, VIN = 0V -5 µA nPECL_CLK V DD = 3.6V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0 .31 V VCMR Common Mode Input Voltage; NOTE 1, 2 1 .5V DD V NOTE 1: Common mode voltage is defi ned as VIH. NOTE 2: For single ended applications, the maximum input voltage for PECL_CLK and nPECL_CLK is VDD + 0.3V. NOTE : Stresses beyond those l isted under Absolute Maximum Rat ings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these cond itions or any cond itions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4 .6V Inputs, V I -0 .5V to VDD + 0.5V Outputs, I O Cont inuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 37 .8°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C

NOTE 1: For single ended applications, the maximum input voltage for HSTL_CLK and nHSTL_CLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. NOTE 3: Outputs terminated with 50Ω to ground. NOTE 4: Defi ned with respect to output voltage swing at a given condition. All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured from VDD/2 to the output differential crossing point for single ended input levels. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. at the differential cross points. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision A January 21, 20165 PARAMETER MEASUREMENT INFORMATION PART-TO-PART SKEW PROPAGATION DELAY OUTPUT RISE/FALL TIME DIFFERENTIAL INPUT LEVEL OUTPUT SKEW 3.3V CORE/1.6V TO 3.6V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

This section provides information on power dissipation and junction temperature for the 852911I. Equations and example calculations are also provided. The total power dissipation for the 852911I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.6V * 95mA = 342mW
• Power (outputs)MAX = 87.2mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 87.2mW = 784.8mW Total Power_MAX (3.6V, with all outputs switching) = 342mW + 784.8mW = 1126.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1 .127W * 31.1°C/W = 120°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Multi-Layer PCB, JEDEC Standard Test Boards 37 .8°C/W 31 .1°C/W 28 .3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 6. Thermal Resistance θJA for 28-pin PLCC, Forced Convection

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION

TABLE 6. θJAVS. AIR FLOW TABLE FOR 28 LEAD PLCC NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision A January 21, 201615 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 1 Block D iagram - corrected drawing. 5/23/05 AT 8 1 4 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/5/10 AT 8 1 6 Replaced leaded part numbers with Lead-free part numbers. Deleted quantity from Tape & Reel 1/21/14 A Removed ICS from the part number where needed. Updated header and footer. 1/21/16

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