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Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator 85222 DATASHEET 85222 REVISION C 5/7/15 1 ©2015 Integrated Device Technology, Inc. The 85222 is a Dual LVCMOS / LVTTL-to- Differential LVHSTL Translator. The 85222 has two single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to LVHSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. For optimum performance, both output pairs need to be terminated, even if one output pair is unused. GENERAL DESCRIPTION FEATURES

  • 2 differential LVHSTL outputs
  • Selectable CLK0, CLK1 LVCMOS clock inputs
  • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 350MHz
  • Part-to-part skew: 350ps (maximum)
  • Propagation delay: 1.3ns (maximum)
  • V OH: 1.2V (maximum)
  • 3.3V and 2.5V operating supply
  • 0°C to 70°C ambient operating temperature
  • Industrial temperature information available upon request
  • Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT 85222 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View nQ0 nQ1 nQ0 nQ1 CLK0 CLK1 VDD CLK0 CLK1 GND

85222 DATA SHEET

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TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1, 2 Q0, nQ0 Output Differential output pair. LVHSTL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVHSTL interface levels. 5 GND Power Power supply ground. 6 CLK1 Input Pulldown LVCMOS / LVTTL clock input. 7 CLK0 Input Pulldown LVCMOS / LVTTL clock input. DD Power Positive supply pin. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated. Refer to Application Information section for a schematic layout.

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TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDD Positive Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 45 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage CLK0, CLK1 2 V DD + 0.3 V VIL Input Low Voltage CLK0, CLK1 -0.3 1.3 V IIH Input High Current CLK0, CLK1 VDD = VIN = 3.465V, VDD = VIN = 2.625V 150 µA IIL Input Low Current CLK0, CLK1 VDD = VIN = 3.465V, VDD = VIN = 2.625V -5 µA TABLE 3C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 1 1.2 V VOL Output Low Voltage; NOTE 1 VDD = 3.3V ± 5% 0 0.4 V VDD = 2.5V ± 5% 0 0.55 V VSWING Peak-to-Peak Output Voltage Swing VDD = 3.3V ± 5% 0.6 1.2 V VDD = 2.5V ± 5% 0.45 1.2 V NOTE 1: Outputs terminated with 50Ω to GND. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL LVHSTL TRANSLATOR

4 REVISION C 5/7/15

TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tPD Propagation Delay; NOTE 1 ƒ ≤ 350MHz 750 950 1150 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 350 ps tR Output Rise Time 20% to 80% 150 800 ps tF Output Fall Time 20% to 80% 150 800 ps odc Output Duty Cycle ƒ ≤ 150MHz 48 52 % 150 < ƒ ≤ 250MHz 47 53 % 250 < ƒ ≤ 350MHz 45 55 % NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 4B. AC CHARACTERISTICS, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tPD Propagation Delay; NOTE 1 ƒ ≤ 350MHz 850 1075 1300 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 450 ps tR Output Rise Time 20% to 80% 150 800 ps tF Output Fall Time 20% to 80% 150 800 ps odc Output Duty Cycle ƒ ≤ 150MHz 45 55 % 150 < ƒ ≤ 350MHz 40 60 % NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.

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PARAMETER MEASUREMENT INFORMATION 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT PROPAGATION DELAY OUTPUT RISE/FALL TIME 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PART-TO-PART SKEW

DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL LVHSTL TRANSLATOR

6 REVISION C 5/7/15

APPLICATION INFORMATION

Figure 1 shows a schematic example of 85222. In this example, the inputs are driven by 7Ω output LVCMOS drivers with series terminations. The decoupling capacitors should be physically FIGURE 1. 85222 LVHSTL BUFFER SCHEMATIC EXAMPLE

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This section provides information on power dissipation and junction temperature for the 85222. Equations and example calculations are also provided. The total power dissipation for the 85222 is the sum of the core power plus the power dissipated in the load(s). DD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 45mA = 155.9mW
  • Power (outputs)MAX = 78.9mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 78.9mW = 157.8mW Total Power_MAX (3.465V, with all outputs switching) = 155.9mW + 157.8mW = 313.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.314W * 103.3°C/W = 102.4°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION

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  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 2. To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 2. LVHSTL DRIVER CIRCUIT AND TERMINATION

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TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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TABLE 7. PACKAGE DIMENSIONS

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TABLE 8. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL LVHSTL TRANSLATOR

12 REVISION C 5/7/15

Rev Table Page Description of Change Date B T2 Features section - add Lead-Free bullet. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Ordering Information Table - added Lead-Free part number. Updated data sheet format. 3/31/05 BT 8 1 1 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/5/10 Updated datasheet format 12/19/14 C1 Product Discontinuation Notice - PDN CQ-15-03 5/7/15

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.