85211AMI-01LF

85211I-01 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: rdvorak
• PDF pages: 15

Technical content

Low Skew, 1-to-2 Differential-to-HSTL Fanout Buffer 85211I-01 DATASHEET 85211I-01 REVISION B 6/12/15 1 ©2015 Integrated Device Technology, Inc. BLOCK DIAGRAM P IN ASSIGNMENT GENERAL DESCRIPTION The 85211I-01 is a low skew, high performance 1-to-2 Differential-to-HSTL Fanout Buffer The CLK, nCLK pair can accept most standarddifferential input levels.The 85211I-01 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 85211I-01 ideal for those clock distribution applications demanding well defi ned performance and repeatability. For optimal performance, terminate all outputs.

FEATURES

• Two differential HSTL compatible outputs
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1ns (maximum)
• Output crossover Voltage: 0.68V to 0.9V
• Output duty cycle: 49% - 51% up to 266.6MHz
• V OH = 1.4V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS-compliant package
• For functional replacement use 8523 85211I-01 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View nQ0 nQ1 VDD CLK nCLK GND nQ0 nQ1 CLK nCLK PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016

2 REVISION B 6/12/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. CLOCK INPUT FUNCTION TABLE

0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inverting

1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inverting

NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”. 1, 2 Q0, nQ0 Output Differential output pair. HSTL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels. 5 GND Power Power supply ground. Pulldown Inverting differential clock input. VDD/2 default when left fl oating. 7 CLK Input Pulldown Non-inverting differential clock input. 8V DD Power Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 LOW SKEW, 1-TO-2

DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 22 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current nCLK V DD = VIN = 3.465V 150 µA CLK V DD = VIN = 3.465V 150 µA IIL Input Low Current nCLK V DD = 3.465V, VIN = 0V -150 µA CLK V DD = 3.465V, VIN = 0V -5 µA VPP Peak-to-Peak Input Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 V DD - 0.85 V NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. TABLE 4C. HSTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 1.0 1.4 V VOL Output Low Voltage; NOTE 1 0 0.4 V VOX Output Crossover Voltage 0.68 0.9 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 1.4 V NOTE 1: All outputs must be terminated with 50Ω to ground. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, V DD -0.5V to V DD + 0.5 V Outputs, V DD -0.5V to V DD + 0.5V Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

4 REVISION B 6/12/15

TABLE 5. AC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C All parameters measured at 600MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

5 LOW SKEW, 1-TO-2

DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART-TO-PART SKEWOUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME PROPAGATION DELAY PARAMETER MEASUREMENT INFORMATION

LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 85211I-01 DATA SHEET

6 REVISION B 6/12/15

Figure 2 shows a schematic example of 85211I-01. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located near FIGURE 2. 85211I-01 HSTL BUFFER SCHEMATIC EXAMPLE

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

7 LOW SKEW, 1-TO-2

DIFFERENTIAL-TO-HSTL FANOUT BUFFER CLOCK INPUT INTERFACE The CLK /nCLK accepts differential input signals of both VSWING and VOH to meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the 85211I-01 clock input driven by most common driver types. The input interfaces suggested here are examples only. Please consult with FIGURE 3A. 85211I-01 CLK/ NCLK INPUT DRIVEN BY HSTL D RIVER 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK the vendor of the driver components to confi rm the driver termination requirement. For example in Figure 3, the input termination applies for HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. FIGURE 3B. 85211I-01 CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL D RIVER (INTERFACE 1) FIGURE 3C. 85211I-01 CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL D RIVER (INTERFACE 2) 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V FIGURE 3D. 85211I-01 CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL D RIVER WITH AC COUPLE 125 LVPECL HiPerClockS CLK nCLK R5,R6 locate near the driv er pin. Zo = 50 Ohm 3.3V 3.3V 125 100-200 Zo = 50 Ohm 100-200 3.3V Input RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: HSTL OUTPUT All unused HSTL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

8 REVISION B 6/12/15

This section provides information on power dissipation and junction temperature for the 85211I-01. Equations and example calculations are also provided. The total power dissipation for the 85211I-01 is the sum of the core power plus the power dissipated in the load(s). DD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 22mA = 76.2mW
• Power (outputs)MAX = 82.34mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 82.34mW = 164.7mW Total Power_MAX (3.465V, with all outputs switching) = 76.2mW + 164.7mW = 240.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.241W * 103.3°C/W = 110°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION

9 LOW SKEW, 1-TO-2

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 4. To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 4. HSTL DRIVER CIRCUIT AND TERMINATION

10 REVISION B 6/12/15

TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

11 LOW SKEW, 1-TO-2

TABLE 8. PACKAGE DIMENSIONS

12 REVISION B 6/12/15

TABLE 9. ORDERING INFORMATION

13 LOW SKEW, 1-TO-2

DIFFERENTIAL-TO-HSTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page Description of Change Date A 1 Throughout data sheet changed LVHSTL to HSTL. Changed nCLK Type from VDD/2 to Pullup/Pulldown. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Changed RPULLUP to RPULLUP/RPULLDOWN, Pullup/Pulldown Resistors. 7/16/03 A Features section - added Lead Free/RoHS bullet. Added Recommendations for Unused Output Pins. Ordering Information Table - added Lead-Free part number and marking. 11/01/05 BT 9 1 2 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/4/10 BT 9 Features Section - removed reference to leaded devices. Ordering Information - removed leaded devices. Updated data sheet format. 6/12/15 B T9 12 Product Discontinuation Notice - Last time buy expires September 7, 2016. PDN N-16-02. Ordering Information - Deleted LF note below table. 3/10/16

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