851S201CKILF | DigiCamel IC Datasheet

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Technical content

Features

Two differential HCSL output pairs
Two selectable differential clock input pairs
CLKx, nCLKx pairs can accept HCSL level inputs
Low level input detection on selected input (latched)
Maximum Input frequency: 250MHz
Output skew: 5ps (typical)
Propagation delay: 1.4ns (typical)
Additive RMS phase jitter at 133.33MHz (12kHz - 20MHz): 0.151ps (typical)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging Pin Assignment ICS851S201I 16-Lead VFQFN Top View nQ0 LLA CLK_SEL CLK0 nCLK0 0 Pulldown Pullup/Pulldown Pulldown Pulldown IREF LLAR nQ1 CLK1 nCLK1 Pulldown Pullup/Pulldown 5 6 7 8 16 15 14 13 CLK0 nCLK0 CLK1 nCLK1 nQ0 nQ1 VDD LLAR LLA GND CLK_SEL IREF VDD GND

ICS851S201CKI MAY 27, 2017 2 ©2017 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK0 Input Pulldown Non-inverting differential HCSL clock input. Pulldown Inverting differential HCSL clock input. VDD/2 default when left floating. 3 CLK1 Input Pulldown Non-inverting differential HCSL clock input. DD/2 default when left floating. 5, 13 V DD Power Positive supply pins. allow LLA to set. LVCMOS/LVTTL interface levels. selected differential input (latched). 8, 16 GND Power Power supply ground. 9, 10 Q1, nQ1 Output Differential output pair. HCSL interface levels. 11, 12 Q0, nQ0 Output Differential output pair. HCSL interface levels.

14 IREF Input External fixed precision resistor (475from this pin to ground provides a

reference current used for differential current-mode Qx, nQx clock outputs. selects CLK0, nCLK0 inputs. LVCMOS/LVTTL interface levels.

ICS851S201CKI MAY 27, 2017 3 ©2017 Integrated Device Technology, Inc. ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER Function Tables Table 3A. Low Level Alarm Function Table NOTE: Input amplitude that is <550mV and >325mV will not reliably cause the LLA output to go HIGH. Input amplitude that is <325mV will always flag the LLA output HIGH. NOTE: Logic High, logic Low, and a differential short on the inputs will cause the LLA output to go HIGH. This feature is only available when both differential inputs are being used, and their respective frequencies are within ±50% of one another (i.e.: CLK0 is 100MHz, CLK1 must be within 50MHz to 150MHz). Table 3B. Control Input Function Table Valid Input Level on Selected Input LLAR LLA VIH  550mV 0 LOW (default) VIH  325mV 0 HIGH n/a 1 Forced LOW CLK_SEL Input Selected

0 CLK0, nCLK0 (default)

1 CLK1, nCLK1

ICS851S201CKI MAY 27, 2017 4 ©2017 Integrated Device Technology, Inc. ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%; TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5%; TA = -40°C to 85°C NOTE 1: See Parameter Measurement Information Section, 3.3V Output Load Test Circuit diagram. Table 4C. DC Characteristics, VDD = 3.3V±5%; TA = -40°C to 85°C NOTE 1: Common mode input voltage is defined at the cross point. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 74.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current unloaded outputs 44 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2.2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current LLAR, CLK_SEL VDD = VIN = 3.465V 150 μA IIL Input Low Current LLAR, CLK_SEL VDD = 3.465V, VIN = 0V -10 μA VOH Output High Voltage LLA; NOTE 1 2.6 V VOL Output Low Voltage LLA; NOTE 1 0.5 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK0, CLK1, nCLK0, nCLK1 VDD = VIN = 3.465V 150 μA IIL Input Low Current CLK0, CLK1 V DD = 3.465V, VIN = 0V -10 μA nCLK0, nCLK1 V DD = 3.465V, VIN = 0V -150 μA VPP Peak-to-Peak Voltage 150 1300 mV VCMR Common Mode Input Voltage; NOTE 1 GND – 0.5 V DD – 0.85 V

ICS851S201CKI MAY 27, 2017 5 ©2017 Integrated Device Technology, Inc. Table 5. AC Characteristics, VDD = 3.3V±5%; TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ  250MHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: Measurement taken from differential waveform. through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section. NOTE 7: Measurement taken from single ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. points for this measurement. See Parameter Measurement Information Section. CROSS for any particular system. See Parameter Measurement Information Section. NOTE 13: Qx, nQx output measured differentially. See Parameter Measurement Information for MUX Isolation diagram.

ICS851S201CKI MAY 27, 2017 6 ©2017 Integrated Device Technology, Inc. ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER Parameter Measurement Information Output Load AC Test Circuit Differential Input Level Part-to-Part Skew Output Load AC Test Circuit Output Skew MUX Isolation HCSL GND 0V 0V SCOPE IREF 3.3V±5% This load condition is used for IDD, tjit, tsk(pp), tsk(o) and tPD measurements. VDD GND nCLKx CLKx t sk(pp) Part 1 Part 2 nQx Qx nQx Qx 475Ω 33Ω 50Ω 50Ω33Ω 49.9Ω 49.9Ω HCSL GND 2pF 2pF Qx nQx IREF 3.3V±5% nQx Qx nQx QxAmplitude (dB) Spectrum of Output Signal Q MUX_ISOL = A0 – A1 (fundamental) Frequencyƒ MUX selects static input MUX selects active input clock signal

ICS851S201CKI MAY 27, 2017 7 ©2017 Integrated Device Technology, Inc. ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER Parameter Measurement Information, continued Propagation Delay Differential Measurement Points for Duty Cycle/Period Single-ended Measurement Points for Absolute Cross Point and Swing Single-ended Measurement Points for Delta Cross Point Output Rise/Fall Edge Rate tPD nQx Qx nCLKx CLKx

ICS851S201CKI MAY 27, 2017 9 ©2017 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS851S201CKI MAY 27, 2017 11 ©2017 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS851S201I. Equations and example calculations are also provided. The total power dissipation for the ICS851S201I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

Power (core) MAX = VDD_MAX * IDD = 3.465V * 44mA = 152.46mW
Power (HCSL) MAX = 2 * 44.5mW = 89mW Total Power_MAX = 152.46mW + 89mW = 241.46mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.242W * 74.7°C/W = 103°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection

Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. Figure 6. HCSL Driver Circuit and Termination use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX.

Ordering Information

Table 9. Ordering Information

ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER 17©2017 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual p roperty rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com Revision History Sheet Rev Table Page Description of Change Date A AMR T4B Supply Voltage, V DD = 4.6V. Note 1: Deleted ‘Outputs terminated with 50to VDD/2.’. Output Duty Cycle: 47%(Min), 53%(Max). MUX ISOL: -65dB (Min) B - 14 Updated the package outline drawings. 5/27/2017

Product Information

851S201CKILF specifications and overview.

Summary

2:1 Differential-to-HCSL Multiplexer with Low Input Level Alarm

Description

2:1 Differential-to-HCSL Multiplexer with Low Input Level Alarm

Source title 851S201CKILF Datasheet(PDF) - Integrated Device Technology

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