ICS8516I IDT | Alldatasheet

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Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip ICS8516I ICS8516I REVISION B SEPTEMBER 10, 2009 1  2009 Integrated Device Technology, Inc. DATA SHEET GENERAL DESCRIPTION The ICS8516I is a low skew, high performance 1- to-16 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8516I CLK, nCLK pair can accept any differ- ential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516I provides a low power, low noise, point-to-point solu- tion for distributing clock signals over controlled impedances of 100 Ω . Dual output enable inputs allow the ICS8516I to be used in a 1-to-16 or 1-to-8 input/output mode. Guaranteed output and part-to-part skew specifications make the ICS8516I ideal for those applications demanding well defined performance and repeatability. BLOCK DIAGRAM PIN ASSIGNMENT

FEATURES

  • Sixteen Differential LVDS outputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 700MHz
  • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks
  • Translates any single-ended input signal to LVDS with resistor bias on nCLK input
  • Multiple output enable inputs for disabling unused outputs in reduced fanout applications
  • LVDS compatible
  • Output skew: 65ps (maximum)
  • Part-to-part skew: 550ps (maximum)
  • Propagation delay: 2.4ns (maximum)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS 48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top ViewOE1 OE2 CLK nCLK nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 nQ9 nQ8 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 VDD nQ5 nQ4 VDD GND nQ3 nQ2 VDD VDD nQ10 Q10 nQ11 Q11 VDD GND nQ12 Q12 nQ13 Q13 VDD nQ14 Q14 nQ15 Q15 GND CLK nCLK GND nQ0 nQ1 ICS8516I nQ9 nQ8 GND OE2 OE1 GND nQ7 nQ6

ICS8516I REVISION B SEPTEMBER 10, 2009 2  2009 Integrated Device Technology, Inc. TABLE 1. PIN DESCRIPTIONS

ICS8516I REVISION B SEPTEMBER 10, 2009 3  2009 Integrated Device Technology, Inc. TABLE 2. PIN CHARACTERISTICS

1 EO2 EO7 Q : 0Q7 Q n : 0 Qn5 1 Q : 8Q5 1 Q n : 8 Q n

00 Z iHZ iHZ iHZ i H

10 E V I T CAE V I T CAZ iHZ i H

01 Z iHZ iHE V I T CAE V I T C A

11 E V I T CAE V I T CAE V I T CAE V I T C A

10 H G IHW OLl a i t n e r e f f i D o t l a i t n e r e f f iDg n i t r e v n I n o N

01 E T O N ; d e s a iBW OLH G IHl a i t n e r e f f i D o t d e d n E e l g n iSg n i t r e v n I n o N

11 E T O N ; d e s a iBH G IHW OLl a i t n e r e f f i D o t d e d n E e l g n iSg n i t r e v n I n o N

1 E T O N ; d e s a iB0 HG IHW OLl a i t n e r e f f i D o t d e d n E e l g n iSg n i t r e v n I

1 E T O N ; d e s a iB1 WOLH G IHl a i t n e r e f f i D o t d e d n E e l g n iSg n i t r e v n I

ICS8516I REVISION B SEPTEMBER 10, 2009 4  2009 Integrated Device Technology, Inc. ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U V D D e g a t l o V y l p p u S e v i t i s o P 5 3 1 .33 .35 6 4 .3V I D D t n e r r u C y l p p u S r e w o P c i t a t SRL 0 0 1 =Ω 5 81A m d a o L oN0 8A m l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U I H I t n e r r u C h g i H t u p n IK LCV N I V =D D V 5 6 4 . 3=0 51A µ K L CnV N I V =D D V 5 6 4 . 3=5 Aµ I L I t n e r r u C w o L t u p n IK LCV D D V , V 5 6 4 . 3 =N I V 0=5 -A µ K L CnV D D V , V 5 6 4 . 3 =N I V 0=0 5 1-A µ V P P e g a t l o V k a e P - o t - k a e P 5 1 .03 .1V V R M C ; e g a t l o V t u p n I e d o M n o m m o C 2 , 1 E T O N 5 . 0 + D NGV D D 5 8 . 0-V V s i K L C n , K L C r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d ed n e e l g n i s r o F : 1 E T O N D D . V 3 . 0 + t s a d e n i f e d s i e g a t l o v e d o m n o m m o C : 2 E T ONV H I. l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U V H I e g a t l o V h g i H t u p nI2 E O , 1 EO2 V D D 3 . 0+V V L I e g a t l o V w o L t u p nI2 E O , 1 EO3 . 0-8 .0V I H I t n e r r u C h g i H t u p nI2 E O , 1 EOV D D V =N I V 5 6 4 . 3=5 Aµ I L I t n e r r u C w o L t u p nI2 E O , 1 EOV D D V , V 5 6 4 . 3 =N I V 0=0 5 1-A µ ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θ JA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability.

ICS8516I REVISION B SEPTEMBER 10, 2009 5  2009 Integrated Device Technology, Inc. TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C

ICS8516I REVISION B SEPTEMBER 10, 2009 6  2009 Integrated Device Technology, Inc. ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ADDITIVE PHASE JITTER Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 148fs typical -50 -60 -70 -80 -90 -100 -100 -120 -130 -140 -150 -160 1k 10k 100k 1M 10M 100M The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

ICS8516I REVISION B SEPTEMBER 10, 2009 7  2009 Integrated Device Technology, Inc. ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP PARAMETER MEASUREMENT INFORMATION PART-TO-PART SKEW PROPAGATION DELAY OUTPUT RISE/FALL TIME 20% 80% 80% 20% tR tF VOD t sk(o) nQx nQ nQy Qy DIFFERENTIAL INPUT LEVEL OUTPUT SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx nQx LVDS 3.3V±5% POWER SUPPL Y +– Float GND VCMR Cross Points VPP GND CLK nCLK VDD t sk(pp) nQx Qx nQy Qy PART 1 PART 2 nCLK CLK nQ0:nQ15 Q0:Q15 tPD nQ0:nQ15 Q0:Q15

ICS8516I REVISION B SEPTEMBER 10, 2009 8  2009 Integrated Device Technology, Inc. ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD OFFSET VOLTAGE tPW tPERIOD tPW tPERIOD odc = x 100% nQ0:nQ15 Q0:Q15 POWER OFF LEAKAGE DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT OUTPUT SHORT CIRCUIT CURRENT DIFFERENTIAL OUTPUT VOLTAGE out out LVDSDC Input ➤ VOS/∆ VOS VDD 100 out out LVDSDC Input VOD/∆ VOD VDD out out LVDSDC Input IOSD VDD out LVDSDC Input IOS IOSB VDD out LVDS IOFF VDD PARAMETER MEASUREMENT INFORMATION, CONTINUED

ICS8516I REVISION B SEPTEMBER 10, 2009 12  2009 Integrated Device Technology, Inc. are used, it is recommended to terminate the unused outputs. FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

ICS8516I REVISION B SEPTEMBER 10, 2009 13  2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8516I. Equations and example calculations are also provided. The total power dissipation for the ICS8516I is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results.

  • Power_ MAX = V DD_MAX * I DD_MAX = 3.465V * 185mA = 641mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + T A Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming no air flow of and a multi-layer board, the appropriate value is 47.9°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (multi-layer).

TABLE 6. THERMAL RESISTANCE θ θθ θθ JA FOR 48-PIN LFQP, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8516I REVISION B SEPTEMBER 10, 2009 14  2009 Integrated Device Technology, Inc. TABLE 7. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8516I REVISION B SEPTEMBER 10, 2009 15  2009 Integrated Device Technology, Inc. TABLE 8. PACKAGE DIMENSIONS

ICS8516I REVISION B SEPTEMBER 10, 2009 16  2009 Integrated Device Technology, Inc. reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 9. ORDERING INFORMATION

ICS8516I REVISION B SEPTEMBER 10, 2009 17  2009 Integrated Device Technology, Inc. ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP T E E H S Y R O T S I H N O I S I V E R v eRe l b aTe g aPe g n a h C f o n o i t p i r c s eDe t a D A 8T2 1. s r e b m u n t r a p e e r F - d a e L d e d d a - e l b a T n o i t a m r o f n I g n i re d r O 4 0 / 0 3 / 7 B 5 T 3 1 . t e l l u b e e r f - d a e L d e d d a - n o i t c e s s e r u t a e F . c e p s r e t t i j e s a h p e v i t i d d a d e d d a - s c i t s i r e t c a r a h C C A . t o l P r e t t i J e s a h P e v i t i d d A d e d d A . s n i P t u p t u O & t u p n I d e s u n U r o f s n o i t a d n e m m o c e R d e d d A . s n o i t a r e d i s n o C r e w o P d e d d A 9 0 / 2 1 / 1 B 31. h p a r g a r a P t s r i F e r u t a r e p m e T n o i t c n u J d e c a l p e R . t a m r o f w e n o t s r e t o o F d n a s r e d a e H d e t a d p U9 0 / 0 1 / 9

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San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP