ICS8512061I IDT | Alldatasheet
Document overview
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- PDF pages: 17
Technical content
Features
- One HCSL output pair and one LVCMOS/LVTTL output
- One single-ended LVCMOS/LVTTL signal input
- LVTTL I/O signal: up to 250MHz
- HCSL interface pins in high impedance state when the device is powered down
- Power-up and power-down glitch-free
- Additive Phase Jitter, RMS: 0.23ps (typical)
- Full 3.3V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package HiPerClockS™ ICS Block Diagram Pin Assignment QA nQA IN DIR_SEL IREF QB HCSL Interface Pullup Pulldown ICS8512061I
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body G Package Top View GND QB DIR_SEL IN QA nQA VDD IREF
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. 1 GND Power Power supply ground. 2 QB Output Single-ended output. LVCM OS/LVTTL interface levels.
3 DIR_SEL Input Pulldown
IN-to-QA/nQA path. When LOW, selects the QA/nQA-to-QB path. LVCMOS/LVTTL interface levels. 4 IN Input Pullup Single-ended signal input. LVCMOS/LVTTL interface levels.
5 IREF Input An external fixed precision resistor (475
reference current used for differential current-mode QA/nQA outputs. 6V DD Power Power supply pin. 7, 8 nQA, QA Output Differential transceiver pair. HCSL interface levels.
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 3 ICS8512061AGI REV. B NOVEMBER 19, 2008 Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, Output Load Test Circuit diagram. Table 3C. Differential DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4A. LVTTL (QB) Output Mode, Receiver AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE 1: Measured from VDD/2 input cross point to the output at VDD/2. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IN V DD = VIN = 3.6V 5 µA DIR_SEL V DD = VIN = 3.6V 150 µA IIL Input Low Current IN V DD = 3.6V, VIN = 0V -150 µA DIR_SEL V DD = 3.6V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 QB V DD = 3.6V 2.6 V VOL Output Low Voltage; NOTE 1 QB V DD = 3.6V 0.5 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VPP Peak-to-Peak Voltage; NOTE 1 DIR_SEL = 0 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 DIR_SEL = 0 GND + 0.5 V DD – 0.85 V Symbol Parameter Test Conditions Minimum Typical Maximum Units FMAX Output Frequency 250 MHz tPD Propagation Delay, NOTE 1 QA/nQA to QB 1.7 2.5 ns tjit Buffer Additive Phase Jitter, RMS 100MHz, Integration Range: 12kHz – 20MHz 0.23 ps tR/tF Output Rise/Fall Time 20% - 80% 200 700 ps odc Output Duty Cycle 40 60 %
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 4 ICS8512061AGI REV. B NOVEMBER 19, 2008 Table 4B. HCSL (QA/nQA) AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 input cross point to the differential output crossing point. NOTE 2: Measurement taken from differential waveform. NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from QA minus nQA). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. NOTE 4: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section. NOTE 5: Measurement taken from single-ended waveform. NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of QA equals the Falling edge of nQA. See Parameter Measurement Information Section NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 10: Defined as the total variation of all crossing voltage of Rising QA and Falling nQA. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 11: Input duty cycle must be 50%. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tjit Buffer Additive Phase Jitter, RMS 100MHz, Integration Range: 12kHz – 20MHz 0.29 ps tPD Propagation Delay, NOTE 1 IN to QA/nQA 1.1 1.7 ns Rise Edge Rate Rising Edge Rate; NOTE 2, 3 0.6 4.0 V/ns Fall Edge Rate Falling Edge Rate; NOTE 2, 3 0.6 4.0 V/ns Vrb Ringback Voltage; NOTE 2, 4 -100 100 V VMAX Absolute Max Output Voltage; NOTE 5, 6 1150 mV VMIN Absolute Min Output Voltage; NOTE 5, 7 -300 mV V CROSS Absolute Crossing Voltage; NOTE 5, 8, 9 250 550 mV ∆VCROSS Total Variation of VCROSS over all edges; NOTE 5, 8, 10 140 mV odc Output Duty Cycle; NOTE 11 45 55 %
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 5 ICS8512061AGI REV. B NOVEMBER 19, 2008 Additive Phase Jitter (HCSL) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.29ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 6 ICS8512061AGI REV. B NOVEMBER 19, 2008 Additive Phase Jitter (LVCMOS) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.23ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 7 ICS8512061AGI REV. B NOVEMBER 19, 2008 Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit Differential Propagation Delay Differential Measurement Points for Rise/Fall Time 3.3V LVCMOS Output Load AC Test Circuit LVCMOS Propagation Delay Differential Measurement Points for Ringback 475Ω 33Ω 50Ω 50Ω33Ω 49.9Ω 49.9Ω HCSL GND 2pF 2pF Qx nQx IREF VDD 3.3V±0.3V tPD VDD QA IN nQA Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate SCOPE Qx LVCMOS GND VDD 1.65V±0.15V -1.65V±0.15V t PD VDD nQA QB QA TSTABLE VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V VRB TSTABLE
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 8 ICS8512061AGI REV. B NOVEMBER 19, 2008 Parameter Measurement Information, continued Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point/Swing Differential Measurement Points for Duty Cycle/Period Q nQ VCROSS_DELTA = 140mV nQ Q VCROSS_MAX = 550mV VCROSS_MIN = 250mV VMAX = 1.15V VMIN = -0.30V Q/nQ 0.0V Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) Clock Period (Differential)
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 9 ICS8512061AGI REV. B NOVEMBER 19, 2008
Application Information
Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins has internal pull-ups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: Differential Outputs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Output All unused LVCMOS output can be left floating. There should be no trace attached.
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 11 ICS8512061AGI REV. B NOVEMBER 19, 2008 Power Considerations (HCSL Outputs) This section provides information on power dissipation and junction temperature for the ICS8512061I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8512061I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = VDD_MAX * IDD_MAX= 3.6V *20mA = 72mW Power (outputs) MAX = 46.8mW/Loaded Output pair Total Power_MAX = 72mW + 46.8mW = 118.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 5A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 5A. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection θJA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5 123.5
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 2. Figure 2. HCSL Driver Circuit and Termination dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX.
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 13 ICS8512061AGI REV. B NOVEMBER 19, 2008 Power Considerations (LVCMOS Outputs) This section provides information on power dissipation and junction temperature for the ICS8512061I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8512061I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. Power (core) MAX = VDD_MAX * IDD_MAX= 3.6V *20mA = 72mW Output Impedance R OUT Power Dissipation due to Loading 50Ω to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50Ω + ROUT)] = 3.6V / [2 * (50Ω + 20Ω)] = 25.7mA Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (25.7mA)2 = 13.2mW per output Dynamic Power Dissipation at 250MHz Power (250MHz) = CPD * Frequency * (VDD)2 = 8pF * 250MHz * (3.6V)2 = 25.9mW per output Total Power = Power (core)MAX + Power (ROUT) + Power (250MHz) = 72mW + 13.2mW + 25.9mW = 111.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 5B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 5B. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5 123.5
Table 6. θJA vs. Air Flow Table for a 8 Lead TSSOP Table 7. Package Dimensions
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 15 ICS8512061AGI REV. B NOVEMBER 19, 2008
Ordering Information
Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER IDT™ / ICS™ TRANSCEIVER 16 ICS8512061AGI REV. B NOVEMBER 19, 2008 Revision History Sheet Rev Table Page Description of Change Date B T3C 3 Added Differential DC Characteristics Table. 11/19/08
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