ICS851010 Datasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 16
Technical content
Features
- Ten differential HCSL outputs
- Translates any differential input signal (LVPECL, LVHSTL, LVDS, HCSL) to HCSL levels without external bias networks
- Maximum output frequency: 250MHz
- Output skew: 165ps (maximum)
- Part-to-part skew: 250ps (maximum)
- Output drift: 140ps (maximum)
- VOH: 850mV (maximum)
- Full 3.3V supply voltage
- Available in lead-free (RoHS 6) package
- 0°C to 70°C ambient operating temperature nQ0 nQ1 nQ2 nQ3 nQ4 nQ9 nQ8 nQ7 nQ6 nQ5 CLK nCLK IREF 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nQ0 VDD nQ1 nQ2 VDD nQ7 VDD nQ6 nQ5 VDD GND IREF nQ3 VDD VDD nQ4 VDD nQ8 nCLK CLK GND nQ9 Pin AssignmentBlock Diagram 851010 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 851010 Datasheet1-to-10, Differential HCSL Fanout Buffer
851010 Datasheet
Table 1. Pin Descriptions typically be set with a RREF of 950 which products an IREF of 1.16mA. Figure 1. HCSL Current Mirror and Output Drive 1, 2 Q0, nQ0 Output Differential output pair. Differential HCSL interface levels. 17, 22, 30 VDD Power Positive supply pins. 4, 5 Q1, nQ1 Output Differential output pair. Differential HCSL interface levels. 6, 7 Q2, nQ2 Output Differential output pair. Differential HCSL interface levels. 9, 25 GND Power Power supply ground. 10 IREF Input Reference current input. Used to set the output current. Connect to 950 resistor to ground. 11, 12 Q3, nQ3 Output Differential output pair. Differential HCSL interface levels. 15, 16 Q4, nQ4 Output Differential output pair. Differential HCSL interface levels. 18, 19 Q5, nQ5 Output Differential output pair. Differential HCSL interface levels. 20, 21 Q6, nQ6 Output Differential output pair. Differential HCSL interface levels. 23, 24 Q7, nQ7 Output Differential output pair. Differential HCSL interface levels. 26 CLK Input Non-inverting differential input. 27 nCLK Input Inverting differential clock input. 28, 29 Q8, nQ8 Output Differential output pair. Differential HCSL interface levels. 31, 32 Q9, nQ9 Output Differential output pair. Differential HCSL interface levels.
3©2015 Integrated Device Technology, Inc December 3, 2015 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functio nal operation of product at these conditions or any conditions beyond those listed in the DC Cha racteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 65.7°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Table 2A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C NOTE 1: Measured using 200MHz input frequency. Table 2B. Differential DC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Item Rating Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current; NOTE 1 105 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK, nCLK V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK, nCLK V DD = 3.465V, VIN = 0V 5 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD – 0.85 V
Table 3. HCSL AC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C NOTE 13: Assuming 50% input duty cycle. Data taken at ƒ 200MHz, unless otherwise specified.
5©2015 Integrated Device Technology, Inc December 3, 2015 Parameter Measurement Information HCSL Output Load AC Test Circuit Differential Input Levels Part-to-Part Skew HCSL Output Load AC Test Circuit Output Skew Propagation Delay Measurement Point33Ω 50Ω 50Ω33Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF VDD VDD V CMR Cross Points VPP VDD GND nCLK CLK nQx Qx nQy Qy tsk(pp) Part 1 Part 2 950Ω 50Ω 50Ω HCSL GND SCOPE IREF This load condition is used for IDD,tsk(pp), tjit(Ø), tPD and tsk(o) measurements. 3.3V±5% VDD nQx Qx nQy Qy tPD nCLK CLK nQ[0:9] Q[0:9]
6©2015 Integrated Device Technology, Inc December 3, 2015 Parameter Measurement Information, continued Differential Measurement Points for Duty Cycle/Period Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point and Swing Differential Measurement Points for Rise/Fall Edge Rate
pair should either be left floating or terminated. line impedance. For most 50 applications, R3 and R4 can be 100. guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
8©2015 Integrated Device Technology, Inc December 3, 2015 Differential Clock Input Interface The CLK/nCLK accepts HCSL, LVDS, LVPECL and SSTL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 3F. CLK/nCLK Input Driven by an SSTL Driver 50Ω 50Ω 1.8V Zo = 50Ω Zo = 50Ω CLK nCLK 3.3V LVHSTL IDT LVHSTL Driver Differential Input 125 125 3.3V Zo = 50Ω Zo = 50Ω CLK nCLK 3.3V 3.3V LVPECL Differential Input HCSL *R3 *R4 CLK nCLK 3.3V 3.3V Differential Input 3.3V 100 LVDS CLK nCLK 3.3V Differential Input Zo = 50Ω Zo = 50Ω SSTL 2.5V Zo = 60Ω Zo = 60Ω 2.5V 120 120 120 120 CLK nCLK 3.3V Differential Input
9©2015 Integrated Device Technology, Inc December 3, 2015 Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50 impedance. Figure 4A. Recommended Termination Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50 impedance. Figure 4B. Recommended Termination
Equations and example calculations are also provided. dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 65.7°C/W per Table 4 below. Table 4. Thermal Resistance JA for 32 Lead LQFP, Forced Convection
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 5. Figure 5. HCSL Driver Circuit and Termination use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX.
Table 5. JA vs. Air Flow Table for a 32 Lead LQFP
Table 6. Package Dimensions for 32 Lead LQFP
14©2015 Integrated Device Technology, Inc December 3, 2015
Ordering Information
Table 7. Ordering Information
15©2015 Integrated Device Technology, Inc December 3, 2015 Rev Table Page Description of Change Date A 10 -11 Pin Description Table, IREF description corrected 475ohm resistor to 950ohm. Corrected Output Driver Current and diagram. Added Propagation Delay diagram and corrected HCSL Output Load AC Test Circuit diagram in Parameter Measurement Information section. Updated Wiring the Differential Input to Accept Single-ended Levels. Corrected power dissipation calculation and total power dissipation section. Corrected HCSL Driver Circuit Termination diagram. Updated Package Outline. Converted datasheet format. 8/2/10 A quantity (1000) in the shipping packaging field. Updated datasheet format. 12/3/15
DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify the products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular purpose, an implie d warranty of merchantability, or non-infringement of the intellectual prope rty rights of others. This document is pr esented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involv ing extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2015 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA www.IDT.com