ICS850S1201I IDT | Alldatasheet

Document overview

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Technical content

Features

  • 12:1 single-ended multiplexer
  • Nominal output impedance: 20Ω (VDD = 3.3V)
  • Maximum output frequency: 250MHz
  • Propagation delay: 2.7ns (maximum)
  • Full 3.3V or 2.5V supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package HiPerClockS™ ICS ICS850S1201I 20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram CLK0 CLK_SEL3 CLK_SEL2 CLK_SEL1 OE CLK1 Q Pulldown Pulldown Pulldown Pulldown Pullup Pulldown CLK11 Pulldown PulldownCLK10 CLK_SEL0 Pulldown 1 CLK8 CLK9 CLK10 CLK11 VDD CLK_SEL0 CLK_SEL1 CLK_SEL2 CLK_SEL3 OE CLK7 CLK6 CLK4 CLK5 CLK2 CLK3 CLK1 CLK0 GND Q

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK8 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 2 CLK9 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 3 CLK10 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 4 CLK11 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Input Pulldown Clock select inputs. See Tabl e 3. LVCMOS / LVTTL interface levels. 10 OE Input Pullup Output enable pin for Q output. LVCMOS/LVTTL interface levels. 11 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 12 GND Power Power supply ground. 13 CLK0 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 14 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 15 CLK2 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 16 CLK3 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 17 CLK4 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 18 CLK5 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 19 CLK6 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 20 CLK7 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.

Table 3. Clock Input Function Table

0000 C L K 0

0001 C L K 1

0010 C L K 2

0011 C L K 3

0100 C L K 4

0101 C L K 5

0110 C L K 6

0111 C L K 7

1000 C L K 8

1001 C L K 9

1010 C L K 1 0

1011 C L K 1 1

12:1, SINGLE-ENDED MULTIPLEXER IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER 4 ICS850S1201BGI REV. A AUGUST 15, 2008 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 87.2°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current Output Unterminated 49 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current Output Unterminated 41 mA

12:1, SINGLE-ENDED MULTIPLEXER IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER 5 ICS850S1201BGI REV. A AUGUST 15, 2008 Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: Output terminated with 50Ω to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Input duty cycle must be 50%. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage V DD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V IIH Input High Current CLK[0:11], CLK_SEL[0:3] VDD = VIN = 3.465V or 2.625V 150 µA OE V DD = VIN = 3.465V or 2.625V 10 µA IIL Input Low Current CLK[0:11], CLK_SEL[0:3] VDD = 3.465V or 2.625V, VIN = 0V -10 µA OE V DD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDD = 3.3V ± 5%, IOH = -12mA 2.6 V VDD = 2.5V ± 5%, IOH = -12mA 1.8 V VOL Output Low Voltage; NOTE 1 VDD = 3.3V ± 5% or 2.5V ± 5%, IOL = 12mA 0.5 V Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 1.4 2.7 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz – 20MHz 0.35 ps tsk(i) Input Skew 175 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 600 ps tR / tF Output Rise/Fall Time 20% to 80% 100 500 ps odc Output Duty Cycle; NOTE 4 f ≤ 200MHz 46 54 % f = 250MHz 40 60 % MUXISOLATION MUX Isolation 155.52MHz 43 dB

12:1, SINGLE-ENDED MULTIPLEXER IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER 6 ICS850S1201BGI REV. A AUGUST 15, 2008 Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Input duty cycle must be 50%. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 1.5 2.7 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz – 20MHz 0.32 ps tsk(i) Input Skew 195 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 600 ps tR / tF Output Rise/Fall Time 20% to 80% 80 600 ps odc Output Duty Cycle; NOTE 4 f ≤ 200MHz 46 54 % f = 250MHz 40 60 % MUXISOLATION MUX Isolation 155.52MHz 43 dB

12:1, SINGLE-ENDED MULTIPLEXER IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER 7 ICS850S1201BGI REV. A AUGUST 15, 2008 Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Offset Frequency (Hz) SSB Phase Noise dBc/Hz Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.35ps (typical)

12:1, SINGLE-ENDED MULTIPLEXER IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER 8 ICS850S1201BGI REV. A AUGUST 15, 2008 Parameter Measurement Information 3.3V Output Load AC Test Circuit Part-to-Part Skew Output Duty Cycle/Pulse Width/Period 2.5V Output Load AC Test Circuit Input Skew SCOPE Qx LVCMOS GND VDD 1.65V±5% -1.65V±5% tsk(pp) VDD VDD Part 1 Part 2 Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q SCOPE Qx LVCMOS GND VDD 1.25V±5% -1.25V±5% tPD1 tPD2 tsk(i) = tPD2 – tPD1 tsk (i) CLK2 Q CLK1

12:1, SINGLE-ENDED MULTIPLEXER IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER 9 ICS850S1201BGI REV. A AUGUST 15, 2008 Parameter Measurement Information, continued MUX Isolation Propagation Delay Output Rise/Fall Time Recommendations for Unused Input Pins Inputs: CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. CLKx (static) CLKy CLK_SELy Q Spectrum MUX_ISOL CLKx CLKy t PD VDD VDD CLK0: CLK11 20% 80% 80% 20% tR tF Q

Table 6. θJA vs. Air Flow Table for a 20 Lead TSSOP

12:1, SINGLE-ENDED MULTIPLEXER IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER 11 ICS850S1201BGI REV. A AUGUST 15, 2008

Ordering Information

Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.

12:1, SINGLE-ENDED MULTIPLEXER www.IDT.com © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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