850S1201 IDT | Alldatasheet

Document overview

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Technical content

Features

  • 12:1 single-ended multiplexer
  • Nominal output impedance: 20 (VDD = 3.3V)
  • Maximum output frequency: 250MHz
  • Propagation delay: 2.7ns (maximum)
  • Full 3.3V or 2.5V supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 850S1201 20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram CLK0 CLK_SEL3 CLK_SEL2 CLK_SEL1 OE CLK1 Q Pulldown Pulldown Pulldown Pulldown Pullup Pulldown CLK11 Pulldown PulldownCLK10 CLK_SEL0 Pulldown 1 CLK8 CLK9 CLK10 CLK11 VDD CLK_SEL0 CLK_SEL1 CLK_SEL2 CLK_SEL3 OE CLK7 CLK6 CLK4 CLK5 CLK2 CLK3 CLK1 CLK0 GND Q 12:1 Single-ended Multiplexer 850S1201 Datasheet

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK8 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 2 CLK9 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 3 CLK10 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 4 CLK11 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Input Pulldown Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels. 10 OE Input Pullup Output enable pin for Q output. LVCMOS/LVTTL interface levels. 11 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 12 GND Power Power supply ground. 13 CLK0 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 14 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 15 CLK2 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 16 CLK3 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 17 CLK4 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 18 CLK5 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 19 CLK6 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 20 CLK7 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.

Table 3. Clock Input Function Table

0000 C L K 0

0001 C L K 1

0010 C L K 2

0011 C L K 3

0100 C L K 4

0101 C L K 5

0110 C L K 6

0111 C L K 7

1000 C L K 8

1001 C L K 9

1010 C L K 1 0

1011 C L K 1 1

4©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 87.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current Output Unterminated 49 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current Output Unterminated 41 mA

5©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: Output terminated with 50 to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from V DD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Input duty cycle must be 50%. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V IIH Input High Current CLK[0:11], CLK_SEL[0:3] VDD = VIN = 3.465V or 2.625V 150 µA OE V DD = VIN = 3.465V or 2.625V 10 µA IIL Input Low Current CLK[0:11], CLK_SEL[0:3] VDD = 3.465V or 2.625V, VIN = 0V -10 µA OE V DD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDD = 3.3V ± 5%, IOH = -12mA 2.6 V VDD = 2.5V ± 5%, IOH = -12mA 1.8 V VOL Output Low Voltage; NOTE 1 VDD = 3.3V ± 5% or 2.5V ± 5%, IOL = 12mA 0.5 V Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 1.4 2.7 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz – 20MHz 0.35 ps tsk(i) Input Skew 175 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 600 ps tR / tF Output Rise/Fall Time 20% to 80% 100 500 ps odc Output Duty Cycle; NOTE 4 f  200MHz 46 54 % f = 250MHz 40 60 % MUXISOLATION MUX Isolation 155.52MHz 43 dB

6©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Input duty cycle must be 50%. Symbol Parameter Test Condition s Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 1.5 2.7 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz – 20MHz 0.32 ps tsk(i) Input Skew 195 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 600 ps tR / tF Output Rise/Fall Time 20% to 80% 80 600 ps odc Output Duty Cycle; NOTE 4 f  200MHz 46 54 % f = 250MHz 40 60 % MUXISOLATION MUX Isolation 155.52MHz 43 dB

7©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Offset Frequency (Hz) SSB Phase Noise dBc/Hz Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.35ps (typical)

8©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet Parameter Measurement Information 3.3V Output Load AC Test Circuit Part-to-Part Skew Output Duty Cycle/Pulse Width/Period 2.5V Output Load AC Test Circuit Input Skew SCOPE Qx GND VDD 1.65V±5% -1.65V±5% tsk(pp) VDD VDD Part 1 Part 2 Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q SCOPE Qx GND VDD 1.25V±5% -1.25V±5% tPD1 tPD2 tsk(i) = ⏐tPD2 – tPD1⏐ tsk (i) CLK2 Q CLK1

9©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet Parameter Measurement Information, continued MUX Isolation Propagation Delay Output Rise/Fall Time Recommendations for Unused Input Pins Inputs: CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. CLKx (static) CLKy CLK_SELy Q Spectrum MUX_ISOL CLKx CLKy Q CLK0: CLK11 20% 80% 80% 20% tR tF Q

Table 6. JA vs. Air Flow Table for a 20 Lead TSSOP

11©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet

Ordering Information

Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

12©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016 850S1201 Datasheet Revision History Sheet Rev Table Page Description of Change Date A T5A, T5B 5, 6 AC Characteristics Table - added thermal note. Ordering Information Table - correct Part/Order Number from 850S1201AGILF/T to 850S1201BGILF/T. 1/4/10 B 1 General Description - deleted HiperClocks logo. Throughout the datasheet - deleted “ICS” prefix and “I” suffix from the part number. Updated header/footer. 2/8/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This produ ct is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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