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Technical content
Features
- Ten selectable differential LVPECL or LVDS outputs
- Output frequencies of 625MHz, 312.5MHz, 156.25MHz or 125MHz using a 25MHz crystal.
- Crystal interface designed for a 25MHz, parallel resonant crystal
- Cycle-to-cycle jitter: 25ps (maximum)
- RMS phase jitter at 156.25MHz (1MHz - 20MHz): 0.375ps (typical), LVDS outputs
- Output duty cycle: 53% (maximum)
- Full 3.3V supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) packaging Frequency Table for Bank A, B and C Outputs Crystal Frequency (MHz) M Feedback Divider VCO Freq uency (MHz) Nx Output Divider Output Frequency (MHz) 25 25 625 1 625 25 25 625 2 312.5 25 25 625 4 156.25 25 25 625 5 125
48 Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body Y Package Top View Pin Assignment ICS849S625I 849S625 Data Sheet Crystal-to-LVPECL/LVDS Clock Synthesizer
2©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Block Diagram Phase Detector VCO 575MHz - 630MHz M = ÷25 OSC MR BYPASS SEL_OUT REF_CLK XTAL_IN XTAL_OUT nQA[0:5] nQB[0:1] QB[0:1] QA[0:5] QC[0:1] nQC[0:1] OEA Pullup OEB Pullup SELA[1:0] SELB[0:1] SELC[0:1] 25MHz OEC Pullup Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown NA = ÷1, ÷2, ÷4, ÷5 NC = ÷1, ÷2, ÷4, ÷5 NB = ÷1, ÷2, ÷4, ÷5
Table 1. Pin Descriptions NOTE: Pullup and Pulludown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 3, 12, 31, 46 V EE Power Negative supply pins. SELC1 Input Pulldown Selects the output divider value. See Table 3D. LVCMOS/LVTTL interface levels. active. When logic LOW, the outputs are disabled and forced to HIGH/LOW. LVCMOS/LVTTL interface levels. 7, 48 V CC Power Core supply pins. active. When logic LOW, the outputs are disabled and forced to HIGH/LOW. LVCMOS/LVTTL interface levels. active. When logic LOW, the outputs are disabled and forced to HIGH/LOW. LVCMOS/LVTTL interface levels. SELB1 Input Pulldown Selects the output divider value. See Table 3C. LVCMOS/LVTTL interface levels. 32, 37 VCCO Power Output supply pins. 14, 15 nQC1, QC1 Output Different ial output pair. LVPECL or LVDS interface levels. 16, 17 nQC0, QC0 Output Different ial output pair. LVPECL or LVDS interface levels. 20, 21 nQB1, QB1 Output Different ial output pair. LVPECL or LVDS interface levels. 22, 23 nQB0, QB0 Output Different ial output pair. LVPECL or LVDS interface levels. 25, 26 nQA5, QA5 Output Different ial output pair. LVPECL or LVDS interface levels. 27, 28 nQA4, QA4 Output Different ial output pair. LVPECL or LVDS interface levels. 29, 30 nQA3, QA3 Output Different ial output pair. LVPECL or LVDS interface levels. 33, 34 nQA2, QA2 Output Different ial output pair. LVPECL or LVDS interface levels. 35, 36 nQA1, QA1 Output Different ial output pair. LVPECL or LVDS interface levels. 38, 39 nQA0, QA0 Output Different ial output pair. LVPECL or LVDS interface levels. 40 V CCA Power Analog supply pin. SELA0 Input Pulldown Selects the output divider value. See Table 3B. LVCMOS/LVTTL interface levels. 43 SEL_OUT Input Pulldown Selects between either LVDS or LVPECL output levels. See Table 3A. LVCMOS/LVTTL interface levels. 44 MR Input Pulldown Master Reset. LVCMOS/LVTTL interface levels. 45 BYPASS Input Pulldown PLL BYPASS mode select pin. See Table 3F. LVCMOS/LVTTL interface levels. 47 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Table 2. Pin Characteristics
1 LVPECL
frequency divided by the selected output divider. divided by the selected output divider.
5©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Outputs configured as LVDS (SEL_OUT = 0). NOTE: For the Power Supply Voltage Sequence Information, see Applications Information section. Table 4B. LVPECL Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Outputs configured as LVPECL (SEL_OUT = 1). NOTE: For the Power Supply Voltage Sequence Information, see Applications Information section. Item Rating Supply Voltage, VCC 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, LVPECL IO Continuos Current Surge Current Outputs, LVDS IO Continuos Current Surge Current 50mA 100mA 10mA 15mA Package Thermal Impedance, JA 33.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.16 3.3 V CC V VCCO Output Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 107 mA ICCA Analog Supply Current 16 mA ICCO Output Supply Current 228 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.16 3.3 V CC V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 181 mA ICCA Analog Supply Current 16 mA
6©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4E. LVDS DC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage V CC = 3.3V 2.2 V CC + 0.3 V VIL Input Low Voltage V CC = 3.3V -0.3 0.8 V IIH Input High Current REF_CLK, BYPASS, MR, SELA[1:0], SELB[1:0], SELC[1:0], SEL_OUT V CC = VIN = 3.465V 150 µA OEA, OEB, OEC V CC = VIN = 3.465V 10 µA IIL Input Low Current REF_CLK, BYPASS, MR, SELA[1:0], SELB[1:0], SELC[1:0], SEL_OUT VCC = 3.465V, VIN = 0V -10 µA OEA, OEB, OEC V CC = 3.465V, VIN = 0V -150 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage V CCO – 1.2 V CCO – 0.7 V VOL Output Low Voltage V CCO – 2.0 V CCO – 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 268 475 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.125 1.375 V VOS VOS Magnitude Change 50 mV
7©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Table 5A. LVPECL AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Outputs configured as LVPECL (SEL_OUT = 1). NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. LVDS AC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Outputs configured as LVDS (SEL_OUT = 0). NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency Qx = ÷1 575 625 630 MHz Qx = ÷2 287.5 312.5 315 MHz Qx = ÷4 143.75 156.25 157.5 MHz Qx = ÷5 115 125 126 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 156.25MHz, Integration Range: (1MHz – 20MHz) 0.373 0.422 ps 156.25MHz, Integration Range: (12kHz – 20MHz) 0.694 1.04 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 25 ps t R / tF Output Rise/Fall Time 10% to 90% 65 180 350 ps odc Output Duty Cycle 47 53 % t LOCK PLL Lock Time 130 ms Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency Qx = ÷1 575 625 630 MHz Qx = ÷2 287.5 312.5 315 MHz Qx = ÷4 143.75 156.25 157.5 MHz Qx = ÷5 115 125 126 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 156.25MHz, Integration Range: (1MHz – 20MHz) 0.375 0.413 ps 156.25MHz, Integration Range: (12kHz – 20MHz) 0.712 1.26 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 20 ps t R / tF Output Rise/Fall Time 10% to 90% 65 190 350 ps odc Output Duty Cycle 47 53 % t LOCK PLL Lock Time 130 ms
8©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Typical Phase Noise at 156.25MHz (LVPECL) Typical Phase Noise at 156.25MHz (LVPECL) 156.25MHz RMS Phase Jitter (Random) 1MHz to 20MHz = 0.373ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.694ps (typical) Offset Frequency (Hz)
9©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Typical Phase Noise at 156.25MHz (LVDS) Typical Phase Noise at 156.25MHz (LVDS) Noise Power dBc Hz 156.25MHz RMS Phase Jitter (Random) 1MHz to 20MHz = 0.375ps (typical) Offset Frequency (Hz) Noise Power dBc Hz 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.712ps (typical) Offset Frequency (Hz)
10©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Parameter Measurement Information LVPECL Output Load AC Test Circuit RMS Phase Jitter LVPECL Output Rise/Fall Time LVDS Output Load AC Test Circuit Cycle-to-Cycle Jitter LVDS Output Rise/Fall Time VCC, VCCA -1.3V±0.165V VCCO 10% 90% 90% 10% tR tF VSWING nQAx, nQBx, nQCx QAx, QBx, QCx 3.3V ±5% VCC, VCCO VCCA tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
nQAx, nQBx, nQCx QAx, QBx, QCx 10% 90% 90% 10% tR tF VOD nQAx, nQBx, nQCx QAx, QBx, QCx
11©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup Offset Voltage Setup nQAx, nQBx, nQCx QAx, QBx, QCx
resistor can be tied from the REF_CLK to ground. resistance is not required but can be added for additional protection. should either be left floating or terminated. Table 6. Recommended Crystal Specifications NOTE: External tuning capacitors must be used for proper operation. VCC is applied. The VCCO supply voltage may be applied at any time.
and the inner edges of pad pattern for the leads to avoid any shorts. Enhance Leadframe Base Package, Amkor Technology. Figure 4. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
This section provides information on power dissipation and junction temperature for the 849S625. Equations and example calculations are also provided. The total power dissipation for the 849S625 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 33.1°C/W per Table 7 below. Table 7. Thermal Resistance JA for 48 Lead TQFP, E-Pad, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 6. Figure 6. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
This section provides information on power dissipation and junction temperature for the 849S625. Equations and example calculations are also provided. The total power dissipation for the 849S625 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 33.1°C/W per Table 8 below. Table 8. Thermal Resistance JA for 48 Lead TQFP, E-Pad, Forced Convection
Table 9. JA vs. Air Flow Table for a 48 Lead TQFP, E-Pad
Table 10. Package Dimensions for 48 Lead TQFP, E-Pad
0.20 TAB
22©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet
Ordering Information
Table 11. Ordering Information
23©2015 Integrated Device Technology, Inc December 2, 2015 849S625 Data Sheet Revision History Sheet Rev Table Page Description of Change Date A T4E 6 VOD: changed units from V to mV 10/1/12 T11 22 Deleted quantity from Tape &Rreel. Deleted Lead-Free note.
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