849N202CKI-DDDLFT

ICS849N202I IDT | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 39

Technical content

Features

4TH generation FemtoClock® NG technology
Universal Frequency Translator (UFT) / Frequency Synthesizer
Two outputs, individually programmable as LVPECL or LVDS
Both outputs may be set to use 2.5V or 3.3V output levels
Programmable output frequency: 0.98MHz up to 1,300MHz
Zero ppm frequency translation
Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz
Crystal input frequency range: 16MHz - 40MHz
Two factory-set register configurations for power-up default state
Power-up default configuration pin or register selectable
Configurations customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I2C
I2C Serial interface for register programming
RMS phase jitter at 125MHz, using a 40MHz crystal (12kHz - 20MHz): 510fs (typical), Low Bandwidth Mode (FracN)
RMS phase jitter at 400MHz, using a 40MHz crystal (12kHz - 40MHz): 321fs (typical), Synthesizer Mode (Integer FB)
Output supply voltage modes: VCC/VCCA/VCCO 3.3V/3.3V/3.3V 3.3V/3.3V/2.5V (LVPECL only) 2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 XTAL_IN XTAL_OUT VCC CLK_SEL CLK0 nCLK0 VCC VEE CLK1 nCLK1 LOCK_IND VCC VEE OE0 nQ0 VCCO nQ1 OE1 nc PLL_BYPASS VCC SDATA SCLK CONFIG S_A1 S_A0 nc nc XTALBAD CLK1BAD VCCA VEE LF1 LF0 CLK_ACTIVE nc HOLDOVER CLK0BAD ICS849N202I

40 Lead VFQFN

6mm x 6mm x 0.925mm K Package Top View Pin Assignment

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 2 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Complete Block Diagram ÷N[10:0] ÷M1[16:0] PD/CP ÷P[16:0] CS Output Divider CLK0 CLK1 CLK_SEL LOCK_IND CLK0BAD CLK1BAD CLK_ACTIVE XTALBADRegister Set 0 Register Set 1 Global Registers Control Logic OTP SCLK, S_A0, S_A1 SDATA POR CONFIG HOLDOVER Status Indicators RS CP LF1 LF0 nCLK1 nCLK0 OE0 OE1 nQ0 nQ1 PD/LF ÷M_INT [7:0] ÷M_FRAC [17:0] ADC PLL_BYPASS OSC XTAL_IN XTAL_OUT FemtoClock® NG VCO 1995 - 2600 MHz XTAL Feedback Divider

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 3 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions XTAL_OUT Input Crystal Oscillator interface designed for 12pF parallel resonant crystals. XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output. 3, 7, 13, 29 V CC Power Core supply pins. All must be either 3.3V or 2.5V.

4 CLK_SEL Input Pulldown

5 CLK0 Input Pulldown Non-inverting differential clock input. internal pullup and pulldown resistors). 8, 21, 35 V EE Power Negative supply pins. 9 CLK1 Input Pulldown Non-inverting differential clock input. internal pullup and pulldown resistors). 20, 32 nc Unused No connect. These pins are to be left unconnected.

12 PLL_BYPASS Input Pulldown

edge of the input reference. LVCMOS/LVTTL interface levels. 14 SDATA I/O Pullup I 2C Data Input/Output. Open drain. 15 SCLK Input Pullup I 2C Clock Input. LVCMOS/LVTTL interface levels.

16 CONFIG Input Pulldown

output/input frequency translation ratios, different PLL loop bandwidths, etc. user so desires. LVCMOS/LVTTL interface levels. 17 S_A1 Input Pulldown I 2C Address Bit 1. LVCMOS/LVTTL interface levels. 18 S_A0 Input Pulldown I 2C Address Bit 0. LVCMOS/LVTTL interface levels.

22 OE1 Input Pullup

Active High Output Enable for Q1, nQ1. LVCMOS/LVTTL interface levels. CCO Power Output supply pins for Q1, nQ1 and Q0, nQ0 outputs. Either 2.5V or 3.3V.

28 OE0 Input Pullup

Active High Output Enable for Q0, nQ0. LVCMOS/LVTTL interface levels.

31 CLK_ACTIVE Output

Indicates which of the two differential clock inputs is currently selected. LVCMOS/LVTTL interface levels.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 4 ©2011 Integrated Device Technology, Inc. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 33, 34 LF0, LF1 Input Connection fo r external loop filter components.

37 HOLDOVER Output

38 CLK0BAD Output

Alarm output reflecting the state of CLK0. LVCMOS/LVTTL interface levels.

39 CLK1BAD Output

Alarm output reflecting the state of CLK1. LVCMOS/LVTTL interface levels.

40 XTALBAD Output

Alarm output reflecting the state of XTAL. LVCMOS/LVTTL interface levels.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 5 ©2011 Integrated Device Technology, Inc. mode can be used, without the need for the external crystal. in manual, revertive & non-revertive modes. contact IDT if a specific set of power-up default settings is desired. reset once reconfiguration is complete. using either of the internal configurations. for the values of N applicable to the desired output frequency. Table 3. Output Divider Settings & Frequency Ranges

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 7 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator XTALBAD - indicates if valid edges are being received on the crystal input. Detection is performed by comparing the input to the feedback signal at the upper loop’s Phase / Frequency Detector (PFD). If three edges are received on the feedback without an edge on the crystal input, the XTALBAD alarm is asserted on the pin & register bit. Once an edge is detected on the crystal input, the alarm is immediately deasserted. CLK0BAD - indicates if valid edges are being received on the CLK0 reference input. Detection is performed by comparing the input to the feedback signal at the appropriate Phase / Frequency Detector (PFD). When operating in high-bandwidth mode, the feedback at the upper PFD is used. In low-bandwidth mode, the feedback at the lower PFD is used. If three edges are received on the feedback without an edge on the divided down (÷P) CLK0 reference input, the CLK0BAD alarm is asserted on the pin & register bit. Once an edge is detected on the CLK0 reference input, the alarm is deasserted. CLK1BAD - indicates if valid edges are being received on the CLK1 reference input. Behavior is as indicated for the CLK0BAD alarm, but with the CLK1 input being monitored and the CLK1BAD output pin & register bits being affected. HOLDOVER - indicates that the device is not locked to a valid input reference clock. This can occur in Manual switchover mode if the selected reference input has gone bad, even if the other reference input is still good. In automatic mode, this will only assert if both input references are bad. Input Reference Selection and Switching When operating in Frequency Synthesizer mode, the CLK0 and CLK1 inputs are not used and the contents of this section do not apply. Except as noted below, when operating in either High or Low Bandwidth Frequency Translator mode, the contents of this section apply equally when in either of those modes. Both input references CLK0 and CLK1 must be the same nominal frequency. These may be driven by any type of clock source, including crystal oscillator modules. A difference in frequency may cause the PLL to lose lock when switching between input references. Please contact IDT for the exact limits for your situation. The global control bits AUTO_MAN[1:0] dictate the order of priority and switching mode to be used between the CLK0 and CLK1 inputs. Manual Switching Mode When the AUTO_MAN[1:0] field is set to Manual via Pin, then the ICS849N202I will use the CLK_SEL input pin to determine which input to use as a reference. Similarly, if set to Manual via Register, then the device will use the CLK_SEL register bit to determine the input reference. In either case, the PLL will lock to the selected reference if there is a valid clock present on that input. If there is not a valid clock present on the selected input, the ICS849N202I will go into holdover (Low Bandwidth Frequency Translator mode) or free-run (High Bandwidth Frequency Translator mode) state. In either case, the HOLDOVER alarm will be raised. This will occur even if there is a valid clock on the non-selected reference input. The device will recover from holdover / free-run state once a valid clock is re-established on the selected reference input. The ICS849N202I will only switch input references on command from the user. The user must either change the CLK_SEL register bit (if in Manual via Register) or CLK_SEL input pin (if in Manual via Pin). Automatic Switching Mode When the AUTO_MAN[1:0] field is set to either of the automatic selection modes (Revertive or Non-Revertive), the ICS849N202I determines which input reference it prefers / starts from by the state of the CLK_SEL register bit only. The CLK_SEL input pin is not used in either Automatic switching mode. When starting from an unlocked condition, the device will lock to the input reference indicated by the CLK_SEL register bit. It will not pay attention to the non-selected input reference until a locked state has been achieved. This is necessary to prevent ‘hunting’ behavior during the locking phase. Once the ICS849N202I has achieved a stable lock, it will remain locked to the preferred input reference as long as there is a valid clock on it. If at some point, that clock fails, then the device will automatically switch to the other input reference as long as there is a valid clock there. If there is not a valid clock on either input reference, the ICS849N202I will go into holdover (Low Bandwidth Frequency Translator mode) or free-run (High Bandwidth Frequency Translator mode) state. In either case, the HOLDOVER alarm will be raised. The device will recover from holdover / free-run state once a valid clock is re-established on either reference input. If clocks are valid on both input references, the device will choose the reference indicated by the CLK_SEL register bit. If running from the non-preferred input reference and a valid clock returns, there is a difference in behavior between Revertive and Non-revertive modes. In Revertive mode, the device will switch back to the reference indicated by the CLK_SEL register bit even if there is still a valid clock on the non-preferred reference input. In Non-revertive mode, the ICS849N202I will not switch back as long as the non-preferred input reference still has a valid clock on it. Switchover Behavior of the PLL Even though the two input references have the same nominal frequency, there may be minor differences in frequency and potentially large differences in phase between them. The ICS849N202I will adjust its output to the new input reference. It will use Phase Slope Limiting to adjust the output phase at a fixed maximum rate until the output phase and frequency are now aligned to the new input reference. Phase will always be adjusted by extending the clock period of the output so that no unacceptably short clock periods are generated on the output ICS849N202I.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 8 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Holdover / Free-run Behavior When both input references have failed (Automatic mode) or the selected input has failed (Manual mode), the ICS849N202I will enter holdover (Low Bandwidth Frequency Translator mode) or free-run (High Bandwidth Frequency Translator mode) state . In both cases, once the input reference is lost, the PLL will stop making adjustments to the output phase. If operating in Low Bandwidth Frequency Translation mode, the PLL will continue to reference itself to the local oscillator and will hold its output phase and frequency in relation to that source. Output stability is determined by the stability of the local oscillator in this case. However, if operating in High Bandwidth Frequency Translation mode, the PLL no longer has any frequency reference to use and output stability is now determined by the stability of the internal VCO. If the device is programmed to perform Manual switching, once the selected input reference recovers, the ICS849N202I will switch back to that input reference. If programmed for either Automatic mode, the device will switch back to whichever input reference has a valid clock first. The switchover that results from returning from holdover or free-run is handled in the same way as a switch between two valid input references as described in the previous section. Output Configuration The two outputs of the ICS849N202I both provide the same clock frequency. Both must operate from the same output voltage level of 3.3V or 2.5V, although this output voltage may be less than or equal to the core voltage (3.3V or 2.5V) the rest of the device is operating from. The output voltage level used on the two outputs is supplied on the VCCO pin. The two outputs are individually selectable as LVDS or LVPECL output types via the Q0_TYPE and Q1_TYPE register bits. These two selection bits are provided in each configuration to allow different output type settings under each configuration. The two outputs can be enabled individually also via both register control bits and input pins. When both the OEn register bit and OEn pin are enabled, then the appropriate output is enabled. The OEn register bits default to enabled so that by default the outputs can be directly controlled by the input pins. Similarly, the input pins are provisioned with weak pull-ups so that if they are left unconnected, the output state can be directly controlled by the register bits. When the differential output is in the disabled state, it will show a high impedance condition. Serial Interface Configuration Description The ICS849N202I has an I 2C-compatible configuration interface to access any of the internal registers (Table 4D) for frequency and PLL parameter programming. The ICS849N202I acts as a slave device on the I2C bus and has the address 0b11011xx, where xx is set by the values on the S_A0 & S_A1 pins (see Table 4A for details). The interface accepts byte-oriented block write and block read operations. An address byte (P) specifies the register address (Table 4D) as the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see table 4B, 4C). Read and write block transfers can be stopped after any complete byte transfer. It is recommended to terminate I 2C the read or write transfer after accessing byte #23. For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have a size of 50kΩ typical. Note: if a different device slave address is desired, please contact IDT. Table 4A. I2C Device Slave Address Table 4B. Block Write Operation Table 4C. Block Read Operation

11011 S _ A 1 S _ A 0 R / W

Address W (0) ACK Address Byte (P) ACK Data Byte (P) ACK Data Byte (P+1) ACK Data Byte ... ACK STOP Length (bits) 171 1 8 181 8 1 81 1

Description

W (0) A C K Address Byte (P) A C K Repeate d START Slave Address R (1) A C K Data Byte (P) A C K Data Byte (P+1) A C K Data Byte ... A C KS T O P Length (bits) 17 1 1 8 1 1 7 1 1 8 1 8 1 8 1 1

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 9 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Register Descriptions Please consult IDT for configuration software and/or programming guides to assist in selection of optimal register settings for the desired configurations. Table 4D. I2C Register Map Register Bit Color Key Reg Binary Register Address Register Bit D7 D6 D5 D4 D3 D2 D1 D0 0 00000 MFRAC0[17] MFRAC0[16] MFRAC0[15] MFRAC0[14] MFRAC0[13] MFRAC0[12] MFRAC0[11] MFRAC0[10] 1 00001 MFRAC1[17] MFRAC1[16] MFRAC1[15] MFRAC1[14] MFRAC1[13] MFRAC1[12] MFRAC1[11] MFRAC1[10] 2 00010 MFRAC0[9] MFRAC0[8] MFRAC0[7] MFRAC0[6] MFRAC0[5] MFRAC0[4] MFRAC0[3] MFRAC0[2] 3 00011 MFRAC1[9] MFRAC1[8] MFRAC1[7] MFRAC1[6] MFRAC1[5] MFRAC1[4] MFRAC1[3] MFRAC1[2] 4 00100 MFRAC0[1] MFRAC0[0] MINT0[7] MINT0[6] MINT0[5] MINT0[4] MINT0[3] MINT0[2] 5 00101 MFRAC1[1] MFRAC1[0] MINT1[7] MINT1[6] MINT1[5] MINT1[4] MINT1[3] MINT1[2] 6 00110 MINT0[1] MINT0[0] P0[16] P0[15] P0[14] P0[13] P0[12] P0[11] 7 00111 MINT1[1] MINT1[0] P1[16] P1[15] P1[14] P1[13] P1[12] P1[11] 18 10010 BW0[5] BW0[4] BW0[3] BW0[2] BW0[1] BW0[0] Q1_TYPE0 Q0_TYPE0 19 10011 BW1[5] BW1[4] BW1[3] BW1[2] BW1[1] BW1[0] Q1_TYPE1 Q0_TYPE1 20 10100 MODE_SEL[1] MODE_SEL[0] CONFIG CFG_PIN_REG OE1 OE0 Rsvd Rsvd 21 10101 CLK_SEL AUTO_MAN[1] AUTO_MAN[0] 0 ADC_RATE[1] ADC_RATE[0] LCK_WIN[1] LCK_WIN[0] 22 10110 10 1 0 0 0 0 0 23 10111 CLK_ACTIVE HOLDOVER CLK1BAD CLK0BAD XTAL_BAD LOCK_IND Rsvd Rsvd Configuration 0 Specific Bits Configuration 1 Specific Bits Global Control & Status Bits

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 10 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator The register bits described in Table 4E are duplicated, with one set applying for Configuration 0 and the other for Configuration 1. The functions of the bits are identical, but only apply when the configuration they apply to is enabled. Replace the lowercase n in the bit field description with 0 or 1 to find the field’s location in the bitmap in Table 4D. Table 4E. Configuration-Specific Control Bits Table 4F. Global Control Bits Register Bits Function Q0_TYPEn Determines the output type for output pair Q0, nQ0 for Configuration n. 0 = LVPECL 1 = LVDS Q1_TYPEn Determines the output type for output pair Q1, nQ1 for Configuration n. 0 = LVPECL 1 = LVDS Pn[16:0] Reference Pre-Divid er for Configuration n. M1_n[16:0] Integer Feedback Divider in Lower Feedback Loop for Configuration n. M_INTn[7:0] Feedback Divider, Integer Value in Upper Feedback Loop for Configuration n. M_FRACn[17:0] Feedback Divider, Fractional Value in Upper Feedback Loop for Configuration n. Nn[10:0] Output Divider for Configuration n. BWn[6:0] Internal Operation Settings for Configuration n. Please use IDT ICS849N202I Configuration Software to determine the correct settings for these bits for the specific configuration. Alternatively, please consult with IDT directly for further information on the functions of these bits.The function of these bits are explained in Tables 4J and 4K. Register Bits Function MODE_SEL[1:0] PLL Mode Select 00 = Low Bandwidth Frequency Translator 01 = Frequency Synthesizer 10 = High Bandwidth Frequency Translator 11 = High Bandwidth Frequency Translator CFG_PIN_REG Configuration Control. Selects whether the configuration selection function is under pin or register control. 0 = Pin Control 1 = Register Control CONFIG Configuration Selection. Selects whether the device uses the register configuration set 0 or 1. This bit only has an effect when the CONFIG_PIN_REG bit is set to 1 to enable register control. OE0 Output Enable Control for Output 0. Both this register bit and the corresponding Output Enable pin OE0 must be asserted to enable the Q0, nQ0 output. 0 = Output Q0, nQ0 disabled 1 = Output Q0, nQ0 under control of the OE0 pin OE1 Output Enable Control for Output 1. Both this register bit and the corresponding Output Enable pin OE1 must be asserted to enable the Q1, nQ1 output. 0 = Output Q1, nQ1 disabled 1 = Output Q1, nQ1 under control of the OE1 pin Rsvd Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed AUTO_MAN[1:0] Selects how input clock selection is performed. 00 = Manual Selection via pin only 01 = Automatic, non-revertive 10 = Automatic, revertive 11 = Manual Selection via register only

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 11 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Table 4G. Global Status Bits CLK_SEL In manual clock selection via register mode, this bit will command which input clock is selected. In the automatic modes, this indicates the primary clock input. In manual selection via pin mode, this bit has no effect. 0 = CLK0 1 = CLK1 ADC_RATE[1:0] Sets the ADC sampling rate in Low-Bandwidth Mode as a fraction of the crystal input frequency. 00 = Crystal Frequency / 16 01 = Crystal Frequency / 8 10 = Crystal Frequency / 4 (recommended) 11 = Crystal Frequency / 2 LCK_WIN[1:0] Sets the width of the window in which a new reference edge must fall relative to the feedback edge: 00 = 2usec (recommended), 01 = 4usec, 10 = 8usec, 11 = 16usec Register Bits Function CLK0BAD Status Bit for input clock 0. This function is mirrored in the CLK0BAD pin. 0 = input CLK0 is good 1 = input CLK0 is bad. Self clears when input clock returns to good status CLK1BAD Status Bit for input clock 1. This function is mirrored in the CLK1BAD pin. 0 = input CLK1 is good 1 = input CLK1 is bad. Self clears when input clock returns to good status XTALBAD Status Bit. This function is mirrored on the XTALBAD pin. 0 = crystal input good 1 = crystal input bad. Self-clears when the XTAL clock returns to good status LOCK_IND Status bit. This function is mirrored on the LOCK_IND pin. 0 = PLL unlocked 1 = PLL locked HOLDOVER Status Bit. This function is mirrored on the HOLDOVER pin. 0 = Input to phase detector is within specifications and device is tracking to it 1 = Phase detector input is not within specifications and DCXO is frozen at last value CLK_ACTIVE Status Bit. Indicates which input clock is active. Automatically updates during fail-over switching. Status also indicated on CLK_ACTIVE pin.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 12 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Table 4J. BW[6:0] Bits Table 4K. Functions of Fields in BW[6:0] Table 4L. High Bandwidth Frequency and Frequency Synthesizer Bandwidth Settings NOTE: To achieve 4MHz bandwidth, reference to the phase detector should be 80MHz. Mode BW[6] BW[5] BW[4] BW[3] BW[2] BW[1] BW[0] Synthesizer Mode PLL2_LF[1] PLL2_LF[0] DSM_O RD DSM_EN PLL2_CP[1] PLL2_CP[0] PLL2_LOW_ICP High-Bandwidth Mode PLL2_LF[1] PLL2_LF[0] DSM_O RD DSM_EN PLL2_CP[1] PLL2_CP[0] PLL2_LOW_ICP Low-Bandwidth Mode ADC_GAIN[3] ADC_GAIN[2] ADC_GA IN[1] ADC_GAIN[0] PLL1_CP[1] PLL1_CP[0] PLL2_LOW_ICP Register Bits Function PLL2_LF[1:0] Sets loop filter values for upper loop PLL in Frequency Synthesizer & High-Bandwidth modes. Defaults to setting of 00 when in Low Bandwidth Mode. See Table 4L for settings. DSM_ORD Sets Delta-Sigma Modulation to 2nd (0) or 3rd order (1) operation DSM_EN Enables Delta-Sigma Modulator 0 = Disabled - feedback in integer mode only 1 = Enabled - feedback in fractional mode PLL2_CP[1:0] Upper loop PLL charge pump current settings: 00 = 173µA (defaults to this setting in Low Bandwidth Mode) 01 = 346µA 10 = 692µA 11 = reserved PLL2_LOW_ICP Reduces Charge Pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register settings or high VCO operating frequency (>2.4GHz). ADC_GAIN[3:0] Gain setting for ADC in Low Bandwidth Mode. PLL1_CP[1:0] Lower loop PLL charge pump current settings (lower loop is only used in Low Bandwidth Mode): 00 = 800µA 01 = 400µA 10 = 200µA 11 = 100µA Desired Bandwidth PLL2_CP PLL2_LOW_ICP PLL2_LF Frequency Synthesizer Mode 200kHz 00 1 00 400kHz 01 1 01 800kHz 10 1 10 2MHz 10 1 11 High Bandwidth Frequency Translator Mode 200kHz 00 1 00 400kHz 01 1 01 800kHz 10 1 10 4MHz 10 0 11

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 13 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5A. LVPECL Power Supply DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Table 5B. LVPECL Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to V CC + 0.5V Outputs, VO (LVCMOS) -0.5V to V CCO + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, I O (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 32.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.30 3.3 V CC V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 320 mA ICCA Analog Supply Current 30 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.30 3.3 V CC V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 319 mA ICCA Analog Supply Current 30 mA

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 14 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Table 5C. LVPECL Power Supply DC Characteristics, VCC = VCCO = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Table 5D. LVDS Power Supply DC Characteristics, VCC = VCCO = 3.3V±5%, TA = -40°C to 85°C Table 5E. LVDS Power Supply DC Characteristics, VCC = VCCO = 2.5V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage V CC – 0.26 2.5 V CC V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 304 mA ICCA Analog Supply Current 26 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.30 3.3 V CC V VCCO Output Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 273 mA ICCA Analog Supply Current 30 mA ICCO Output Supply Current 42 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage V CC – 0.26 2.5 V CC V VCCO Output Supply Voltage 2.375 2.5 2.625 V ICC Power Supply Current 263 mA ICCA Analog Supply Current 26 mA ICCO Output Supply Current 42 mA

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 15 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Table 5F. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C Table 5G. Differential DC Characteristics, VCC = VCCO = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C .NOTE 1: Common mode input voltage is defined as the crosspoint voltage. Table 5H. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.3V 2 V CC + 0.3 V VCC = 2.5V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V IIH Input High Current CLK_SEL, CONFIG, PLL_BYPASS, S_A[0:1] VCC = VIN = 3.465V or 2.625V 150 µA OE0, OE1, SCLK, SDATA VCC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current CLK_SEL, CONFIG, PLL_BYPASS, S_A[0:1] VCC = 3.465V or 2.625V, VIN = 0V -5 µA OE0, OE1, SCLK, SDATA VCC = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage HOLDOVER, SDATA CLK_ACTIVE, LOCK_IND, XTALBAD, CLK0BAD, CLK1BAD VCCO = 3.3V ± 5%, IOH = -8mA 2.6 V VCCO = 2.5V ± 5%, IOH = -8mA 1.8 V VOL Output Low Voltage HOLDOVER, SDATA CLK_ACTIVE, LOCK_IND, XTALBAD, CLK0BAD, CLK1BAD V CCO = 3.3V ± 5% or 2.5V ± 5%, IOL = 8mA 0.5 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK0, nCLK0, CLK1, nCLK1 V CC = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK0, CLK1 V CC = 3.465V or 2.625V, VIN = 0V -5 µA nCLK0, nCLK1 V CC = 3.465V or 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1 VEE + 0.5 V CC - 1.0 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CCO – 1.1 V CCO – 0.7 V VOL Output Low Voltage NOTE 1 V CCO – 2.0 V CCO – 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 16 ©2011 Integrated Device Technology, Inc. NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. Table 6. Input Frequency Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C Table 7. Crystal Characteristics

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 17 ©2011 Integrated Device Technology, Inc. Table 8. AC Characteristics, VCC = VCCO = 3.3V±5% or 2.5V±5%, or has been reached under these conditions. NOTE 1: Measured using a Rohde & Schwarz SMA100 Signal Generator, 9kHz to 6GHz as the input source. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 18 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Typical Phase Noise at 400MHz (HBW Mode) 400MHz RMS Phase Jitter 12kHz to 20MHz = 295fs (typical) Noise Power dBc Hz Offset Frequency (Hz)

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 19 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Parameter Measurement Information 3.3 Core/3.3V LVPECL Output Load AC Test Circuit 3.3 Core/2.5V LVPECL Output Load AC Test Circuit 2.5 Core/2.5V LVDS Output Load AC Test Circuit 2.5 Core/2.5V LVPECL Output Load AC Test Circuit 3.3 Core/3.3V LVDS Output Load AC Test Circuit Differential Input Levels SCOPE Qx nQx VEE VCC, -1.3V+0.165V VCCO VCCA SCOPEQx nQx VEE VCC 2.8V±0.04V -0.5V±0.125V VCCA 2.8V±0.04V VCCO SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +– Float GND VCC, VCCO VCCA SCOPE Qx nQx VEE VCC, -0.5V±0.125V VCCA VCCO SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +– Float GND VCCAVCCO VCC, VCMR Cross Points VPP VCC VEE CLKx nCLKx

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 20 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Parameter Measurement Information, continued RMS Phase Jitter Cycle-to-Cycle Jitter LVDS Output Rise/Fall Time Output Skew Period Jitter LVPECL Output Rise/Fall Time Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

20% 80% 80% 20% tR tF VOD nQx Qx Qx Qy nQx nQy tsk(o) VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram 20% 80% 80% 20% tR tF VSWING nQx Qx

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 21 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Parameter Measurement Information, continued Differential Output Duty Cycle/Output Pulse Width/Period Differential Output Voltage Setup Offset Voltage Setup tPW tPERIOD tPW tPERIOD odc = x 100% nQx Qx 100 out out LVDSDC Input VOD/∆ VOD VDD out out LVDSDC Input ➤ VOS/∆ VOS VDD

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 22 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Applications Information Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. CLKx/nCLKx Inputs For applications not requiring the use of either differential input, both CLKx and nCLKx can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLKx to ground. It is recommended that CLKx, nCLKx be left unconnected in frequency synthesizer mode. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 Ω across. If they are left floating there should be no trace attached. LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. Recommended Values for Low-Bandwidth Mode Loop Filter External loop filter components are not needed in Frequency Synthesizer or High-Bandwidth modes. In Low-Bandwidth mode, the loop filter structure and components shown in Figure 11 are recommended. Please consult IDT if other values are needed.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 27 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 8A and 8B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 8A. 3.3V LVPECL Output Termination Figure 8B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 29 ©2011 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Lead frame Base Package, Amkor Technology. Figure 10. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 30 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Schematic Layout Figure 11 (next page), shows an example of the UFT (849N202I) application schematic. Input and output terminations shown are intended as examples only and may not represent the exact user configuration. In this example, the device is operated at VCC = 3.3V. For 2.5V option, please refer to the “Termination for 2.5V LVPECL Outputs” for output termination recommendation. The decoupling capacitors should be located as close as possible to the power pin. A 12pF parallel resonant 16MHz to 40MHz crystal is used in this example. Different crystal frequencies may be used. The C1 = C2 = 5pF are recommended for frequency accuracy. If different crystal types are used, please consult IDT for recommendations. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow either 2-pole or 3-pole filter to be used. The 3-pole filter can be used for additional spur reduction. If a 2-pole filter construction is used, the LF0 and LF1 pins must be tied-together to the filter. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The UFT (849N202I) provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 31 ©2011 Integrated Device Technology, Inc. Figure 11. ICS849N202I Application Schematic Note 3: Other configurations are supported. Please contact IDT for details. compononents required to select default condition.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 32 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS849N202I. Equations and example calculations are also provided. The total power dissipation for the ICS849N202I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 32.4°C/W per Table 9 below. Table 9. Thermal Resistance θJA for 40 Lead VFQFN, Forced Convection

Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 12. Figure 12. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 34 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS849N202I. Equations and example calculations are also provided. The total power dissipation for the ICS849N202I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 32.4°C/W per Table 10 below. Table 10. Thermal Resistance θJA for 40 Lead VFQFN, Forced Convection

Type A: Chamfer on the paddle (near pin 1)
Type C: Mouse bite on the paddle (near pin 1)

Ordering Information

Table 13. Ordering Information NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. NOTE: For the specific -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document. devices or critical medical instruments.

ICS849N202CKI REVISION A SEPTEMBER 26, 2011 38 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Revision History Sheet Rev Table Page Description of Change Date A 18 Phase Jitter Plot Label - corrected int egration range from 12MHz to 12kHz. 9/26/11

ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 We’ve Got Your Timing Solution

Summary

FemtoClock짰 NG Universal Frequency Translator

Description

FemtoClock짰 NG Universal Frequency Translator

Source title 849N202CKI-DDDLFT Datasheet(PDF) - Integrated Device Technology

Read 849N202CKI-DDDLFT online.

ICS849N202I IDT | Alldatasheet

Document overview

Technical content

Features

40 Lead VFQFN

4 CLK_SEL Input Pulldown

12 PLL_BYPASS Input Pulldown

16 CONFIG Input Pulldown

22 OE1 Input Pullup

28 OE0 Input Pullup

31 CLK_ACTIVE Output

37 HOLDOVER Output

38 CLK0BAD Output

39 CLK1BAD Output

40 XTALBAD Output

11011 S _ A 1 S _ A 0 R / W

Description

1000 Cycles

Ordering Information

6024 Silver Creek Valley Road

849N202CKI-DDDLFT specifications and overview.

More parts from the same family.