8487EIB

ISL8487E INTERSIL | Alldatasheet

Document overview

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• PDF pages: 14

Technical content

Features

• Fractional Unit Load Allows up to 256 Devices on the Bus
• Specified for 10% Tolerance Supplies
• Slew Rate Limited Versions for Error Free Data
• Low Current Shutdown Mode (Except ISL81487E). . . 0.5 µA
• Low Quiescent Supply Current:
• -7V to +12V Common Mode Input Voltage Range
• Three State Rx and Tx Outputs
• 30ns Propagation Delays, 5ns Skew (ISL81487E)
• Half Duplex Pinouts
• Operate from a Single +5V Supply (10% Tolerance)
• Current Limiting and Thermal Shutdown for Driver Overload Protection
• Pin Compatible Replacements for: MAX487E, (ISL8487E); LTC1487, ADM1487 (ISL81487L); MAX1487E, ST485ER (ISL81487E)
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• High Node Count Networks
• Automated Utility Meter Reading Systems
• Factory Automation
• Security Networks
• Building Environmental Control Systems
• Industrial/Process Control Networks

TABLE 1. SUMMARY OF FEATURES CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.

2 FN6051.6 Pinout ISL8487E, ISL81487L, ISL81487E (PDIP, SOIC) TOP VIEW

Ordering Information

PART NO. (BRAND) TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL8487EIB* (8487EIB) -40 to 85 8 Ld SOIC M8.15 ISL8487EIBZ* (8487EIB)(Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL8487EIP -40 to 85 8 Ld PDIP E8.3 ISL81487LIB* (81487LIB) -40 to 85 8 Ld SOIC M8.15 ISL81487LIBZ* (81487LIB)(Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL81487LIP -40 to 85 8 Ld PDIP E8.3 ISL81487EIB* (81487EIB) -40 to 85 8 Ld SOIC M8.15 ISL81487EIBZ* (81487EIB)(Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL81487EIP -40 to 85 8 Ld PDIP E8.3 ISL81487EIPZ (ISL81487EIPZ)(Note) -40 to 85 8 Ld PDIP (Pb-free) E8.3 *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. RO RE DE DI VCC B/Z A/Y GND D R Truth Tables TRANSMITTING INPUTS OUTPUTS RE DE DI Z Y X1101 X1010 0 0 X High-Z High-Z 1 0 X High-Z * High-Z * *Shutdown Mode for ISL8487E, ISL81487L (See Note 7) RECEIVING INPUTS OUTPUT RE DE A-B RO 00 ≥ +0.2V 1 00 ≤ -0.2V 0 0 0 Inputs Open 1 10X H i g h - Z * 1 1 X High-Z *Shutdown Mode for ISL8487E, ISL81487L (See Note 7) Pin Descriptions PIN FUNCTION RO Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z hi gh. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y ±15kV HBM ESD Protected, RS-485/422 level, noninverting receiver input and non-inverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1. B/Z ±15kV HBM ESD Protected, RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1. VCC System power supply input (4.5V to 5.5V). ISL8487E, ISL81487L, ISL81487E

3 FN6051.6 Typical Operating Circuits ISL8487E, ISL81487L, ISL81487E 0.1µF D R VCC GND RO RE DE DI A/Y B/Z +5V 0.1µF D R VCC GND RO RE DE DI A/Y B/Z +5V RT RT ISL8487E, ISL81487L, ISL81487E

4 FN6051.6 Absolute Maximum Ratings Thermal Information Input Voltages Input/Output Voltages Short Circuit Duration Operating Conditions Temperature Range Thermal Resistance (Typical, Note 1) θJA (°C/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C, (Note 2) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS DC CHARACTERISTICS Driver Differential V OUT (no load) V OD1 Full - - V CC V Driver Differential VOUT (with load) V OD2 R = 50Ω (RS-422), (Figure 1) Full 2 3 - V R = 27Ω (RS-485), (Figure 1) Full 1.5 2.3 5 V Change in Magnitude of Driver Differential VOUT for Complementary Output States ∆VOD R = 27Ω or 50Ω, (Figure 1) Full - 0.01 0.2 V Driver Common-Mode VOUT VOC R = 27Ω or 50Ω, (Figure 1) Full - - 3 V Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States ∆VOC R = 27Ω or 50Ω, (Figure 1) Full - 0.01 0.2 V Logic Input High Voltage V IH DE, DI, RE Full 2 - - V Logic Input Low Voltage V IL DE, DI, RE Full - - 0.8 V Logic Input Current I IN1 DE, DI, RE Full -2 - 2 µA Input Current (A/Y, B/Z), (Note 10) I IN2 DE = 0V, VCC = 4.5 to 5.5V VIN = 12V Full - - 140 µA VIN = -7V Full - - -120 µA IIN2 DE = 0V, VCC = 0V V IN = 12V Full - - 180 µA VIN = -7V Full - - -100 µA Receiver Differential Threshold Voltage VTH -7V ≤ VCM ≤ 12V Full -0.2 - 0.2 V Receiver Input Hysteresis ∆VTH VCM = 0V 25 - 70 - mV Receiver Output High Voltage V OH IO = -4mA, VID = 200mV Full 3.5 - - V Receiver Output Low Voltage V OL IO = -4mA, VID = 200mV Full - - 0.4 V Three-State (high impedance) Receiver Output Current IOZR 0.4V ≤ VO ≤ 2.4V Full - - ±1 µA Receiver Input Resistance R IN -7V ≤ VCM ≤ 12V Full 96 - - k Ω ISL8487E, ISL81487L, ISL81487E

5 FN6051.6 No-Load Supply Current, (Note 3) I CC ISL81487E, DI, RE = 0V or VCC DE = VCC Full - 400 500 µA DE = 0V Full - 350 420 µA ISL8487E, ISL81487L, DI, RE = 0V or VCC DE = VCC Full - 160 200 µA DE = 0V Full - 120 145 µA Shutdown Supply Current I SHDN (Note 7), DE = 0V, RE = VCC, DI = 0V or VCC Full - 0.5 8 µA Driver Short-Circuit Current, VO = High or Low IOSD1 DE = VCC, -7V ≤ VY or VZ ≤ 12V, (Note 4) Full 35 - 250 mA Receiver Short-Circuit Current I OSR 0V ≤ VO ≤ VCC Full 7 - 85 mA SWITCHING CHARACTERISTICS (ISL81487E) Driver Input to Output Delay t PLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 15 24 50 ns Driver Output Skew t SKEW RDIFF = 54Ω, CL = 100pF, (Figure 2) Full - 3 10 ns Driver Differential Rise or Fall Time t R, tF RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 3 12 25 ns Driver Enable to Output High t ZH CL = 100pF, SW = GND, (Figure 2) Full - 14 70 ns Driver Enable to Output Low t ZL CL = 100pF, SW = VCC, (Figure 2) Full - 14 70 ns Driver Disable from Output High t HZ CL = 15pF, SW = GND, (Figure 2) Full - 44 70 ns Driver Disable from Output Low t LZ CL = 15pF, SW = VCC, (Figure 2) Full - 21 70 ns Receiver Input to Output Delay t PLH, tPHL (Figure 4) Full 30 90 150 ns Receiver Skew | tPLH - tPHL |t SKD (Figure 4) 25 - 5 - ns Receiver Enable to Output High t ZH CL = 15pF, SW = GND, (Figure 5) Full - 9 50 ns Receiver Enable to Output Low t ZL CL = 15pF, SW = VCC, (Figure 5) Full - 9 50 ns Receiver Disable from Output High t HZ CL = 15pF, SW = GND, (Figure 5) Full - 9 50 ns Receiver Disable from Output Low t LZ CL = 15pF, SW = VCC, (Figure 5) Full - 9 50 ns Maximum Data Rate f MAX Full 5 - - Mbps SWITCHING CHARACTERISTICS (ISL8487E) Driver Input to Output Delay t PLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 250 650 2000 ns Driver Output Skew t SKEW RDIFF = 54Ω, CL = 100pF, (Figure 2) Full - 160 800 ns Driver Differential Rise or Fall Time t R, tF RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 250 900 2000 ns Driver Enable to Output High t ZH CL = 100pF, SW = GND, (Figure 3, Note 5) Full 250 1000 2000 ns Driver Enable to Output Low t ZL CL = 100pF, SW = VCC, (Figure 3, Note 5) Full 250 860 2000 ns Driver Disable from Output High t HZ CL = 15pF, SW = GND, (Figure 3) Full 300 660 3000 ns Driver Disable from Output Low t LZ CL = 15pF, SW = VCC, (Figure 3) Full 300 640 3000 ns Receiver Input to Output Delay t PLH, tPHL (Figure 4) Full 250 500 2000 ns Receiver Skew | tPLH - tPHL |t SKD (Figure 4) 25 - 60 - ns Receiver Enable to Output High t ZH CL = 15pF, SW = GND, (Figure 5, Note 6) Full - 10 50 ns Receiver Enable to Output Low t ZL CL = 15pF, SW = VCC, (Figure 5, Note 6) Full - 10 50 ns Receiver Disable from Output High t HZ CL = 15pF, SW = GND, (Figure 5) Full - 10 50 ns Receiver Disable from Output Low t LZ CL = 15pF, SW = VCC, (Figure 5) Full - 10 50 ns Maximum Data Rate f MAX Full 250 - - kbps Time to Shutdown t SHDN (Note 7) Full 50 120 600 ns Driver Enable from Shutdown to Output High tZH(SHDN) CL = 100pF, SW = GND, (Figure 3, Notes 7, 8) Full - 1000 2000 ns Driver Enable from Shutdown to Output Low tZL(SHDN) CL = 100pF, SW = VCC, (Figure 3, Notes 7, 8) Full - 1000 2000 ns Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C, (Note 2) (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS ISL8487E, ISL81487L, ISL81487E

6 FN6051.6 Receiver Enable from Shutdown to Output High tZH(SHDN) CL = 15pF, SW = GND, (Figure 5, Notes 7, 9) Full - 800 2500 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) CL = 15pF, SW = VCC, (Figure 5, Notes 7, 9) Full - 800 2500 ns SWITCHING CHARACTERISTICS (ISL81487L) Driver Input to Output Delay t PLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 150 650 1200 ns Driver Output Skew t SKEW RDIFF = 54Ω, CL = 100pF, (Figure 2) Full - 160 600 ns Driver Differential Rise or Fall Time t R, tF RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 250 900 1200 ns Driver Enable to Output High t ZH CL = 100pF, SW = GND, (Figure 3, Note 5) Full 100 1000 1500 ns Driver Enable to Output Low t ZL CL = 100pF, SW = VCC, (Figure 3, Note 5) Full 100 1000 1500 ns Driver Disable from Output High t HZ CL = 15pF, SW = GND, (Figure 3) Full 150 750 1500 ns Driver Disable from Output Low t LZ CL = 15pF, SW = VCC, (Figure 3) Full 150 750 1500 ns Receiver Input to Output Delay t PLH, tPHL (Figure 4) Full 30 175 250 ns Receiver Skew | tPLH - tPHL |t SKD (Figure 4) 25 - 13 - ns Receiver Enable to Output High t ZH CL = 15pF, SW = GND, (Figure 5, Note 6) Full - 10 50 ns Receiver Enable to Output Low t ZL CL = 15pF, SW = VCC, (Figure 5, Note 6) Full - 10 50 ns Receiver Disable from Output High t HZ CL = 15pF, SW = GND, (Figure 5) Full - 10 50 ns Receiver Disable from Output Low t LZ CL = 15pF, SW = VCC, (Figure 5) Full - 10 50 ns Maximum Data Rate f MAX Full 250 - - kbps Time to Shutdown t SHDN (Note 7) Full 50 140 600 ns Driver Enable from Shutdown to Output High tZH(SHDN) CL = 100pF, SW = GND, (Figure 3, Notes 7, 8) Full - 1100 2000 ns Driver Enable from Shutdown to Output Low tZL(SHDN) CL = 100pF, SW = VCC, (Figure 3, Notes 7, 8) Full - 1000 2000 ns Receiver Enable from Shutdown to Output High tZH(SHDN) CL = 15pF, SW = GND, (Figure 5, Notes 7, 9) Full - 900 2000 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) CL = 15pF, SW = VCC, (Figure 5, Notes 7, 9) Full - 900 2000 ns ESD PERFORMANCE RS-485 Pins (A/Y, B/Z) Human Body Model 25 - ±15 - kV All Other Pins 25 - > ±7-k V NOTES: 2. Currents into device pins are positive; currents out of dev ice pins are negative. Voltages are referenced to ground unless otherwise specified. 3. Supply current specification is valid for loaded drivers when DE = 0V. 4. Applies to peak current. See “Typical Performance Curves” for more information. 5. When testing the ISL8487E and ISL81487L, keep RE = 0 to prevent the device from entering SHDN. 6. When testing the ISL8487E and ISL81487L, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering SHDN. 7. The ISL8487E and ISL81487L are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low-Power Shutdown Mode” section. 8. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN. 9. Set the RE signal high time >600ns to ensure that the device enters SHDN. 10. Devices meeting these limits are denoted as “1/8 unit load (1/8 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus, so there can be 256 1/8 UL devices on a bus. Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C, (Note 2) (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS ISL8487E, ISL81487L, ISL81487E

9 FN6051.6 All the receivers include a “fail-safe if open” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating). Receivers easily meet the data rates supported by the corresponding driver, and receiver outputs are three-statable via the active low RE input. Driver Features The RS-485/422 driver is a differential output device that delivers at least 1.5V across a 54Ω load (RS-485), and at least 2V across a 100Ω load (RS-422). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. Driver outputs are three-statable via the active high DE input. The ISL8487E and ISL81487L driver outputs are slew rate limited to minimize EMI, and to minimize reflections in unterminated or improperly terminated networks. Data rate on these slew rate limited versions is a maximum of 250kbps. ISL81487E drivers are not limited, so faster output transition times allow data rates of at least 5Mbps. Data Rate, Cables, and Terminations RS-485/422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. Devices operating at 5Mbps are limited to lengths less than a few hundred feet, while the 250kbps versions can operate at full data rates with lengths in excess of 1000’. Twisted pair is the cable of choice for RS-485/422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. To minimize reflections, proper termination is imperative when using the 5Mbps device. Short networks using the 250kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. Built-In Driver Overload Protection As stated previously, the RS-485 spec requires that drivers survive worst case bus contentions undamaged. These devices meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never exceeds the RS-485 spec, even at the common mode voltage range extremes. Additionally, these devices utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. In the event of a major short circuit condition, these devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about 15 degrees. If the contention persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. Low Power Shutdown Mode (Excluding ISL81487E) These CMOS transceivers all use a fraction of the power required by their bipolar c ounterparts, but the ISL8487E and ISL81487L include a shutdown feature that reduces the already low quiescent I CC to a 500nA trickle. They enter shutdown whenever th e receiver and driver are simultaneously disabled (RE =V CC and DE = GND) for a period of at least 600ns. Disabl ing both the driver and the receiver for less than 50ns guarantees that shutdown is not entered. Note that receiver and driver enable times increase when enabling from shutdown. Refer to Notes 5-9, at the end of the Electrical Specification table, for more information. ESD Protection All pins on these interface devices include class 3 Human Body Model (HBM) ESD prot ection structures, but the RS-485 pins (driver outputs and receiver inputs) incorporate advanced structur es allowing them to survive ESD events in excess of ±15kV HBM. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply t ouching the port pins, or connecting a cable, can caus e an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection st ructures (e.g., transient suppression diodes), and th e associated, undesirable capacitive load they present. ISL8487E, ISL81487L, ISL81487E

13 FN6051.6 Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A- 0.210 - 5.33 4 A1 0.015 - 0.39 -4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 -5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93 ISL8487E, ISL81487L, ISL81487E

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6051.6 ISL8487E, ISL81487L, ISL81487E Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05