845264

845264 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: epieczon
• PDF pages: 24

Technical content

Features

• Clock generation of: 62.5MHz, 125MHz, 156.25MHz and 312.5MHz
• Two banks of two differential CML clock outputs
• Crystal interface designed for 25MHz, 12pF parallel resonant crystal
• RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.486ps (typical) Offset Single-side Band Phase Noise
• LVCMOS interface levels for the control inputs
• Full 3.3V and 2.5V supply voltage
• Lead-free (RoHS 6) 32 VFQFN packaging
• -40°C to 85°C ambient operating temperature Block Diagram Pin Assignment VCO QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 Phase Detector ÷25 ÷2, ÷4, ÷5, ÷10 1fREF ÷2, ÷4, ÷5, ÷10 OSC nOEA FSELA[1:0] XTAL_IN XTAL_OUT REF_CLK REF_SEL nBYPASS FSELB[1:0] nOEB Pulldown Pulldown Pulldown Pulldown Pullup Pulldown Pulldown 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nQA0 QA0 VDD nOEA nc nc nc nc nQB0 QB0 REF_SEL FSELA1 FSELA0 FSELB1 FSELB0 VDD nc VDDA nBYPASS REF_CLK GND XTAL_OUT XTAL_IN nc QA1 nQA1 GND QB1 nQB1 nOEB nc nc 845264 32 lead, 5mm x 5mm VFQFN

845264 DATA SHEET

Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQA0, QA0 Output Bank A differential clock output pair. CML interface levels. 3, 17 V DD Power Core supply pins. 4 nOEA Input Pulldown Output enable pin for Bank A outputs. See Table 3E for function. LVCMOS/LVTTL interface levels. 16, 25, 32 nc Unused Do not connect. 10 V DDA Power Analog supply pin. 11 nBYPASS Input Pullup PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels. 12 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 13, 29 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. FSELB1 Input Pulldown Output frequency divider select enable pins for Bank B outputs. See Table 3C for function. LVCMOS/LVTTL interface levels. FSELA1 Input Pulldown Output frequency divider select enable pins for Bank A outputs. See Table 3B for function. LVCMOS/LVTTL interface levels. 22 REF_SEL Input Pulldown PLL reference clock select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 23, 24 QB0, nQB0 Output Bank B differential clock output pair. CML interface levels. 26 nOEB Input Pulldown Output enable pin for Bank B outputs. See Table 3F for function. LVCMOS/LVTTL interface levels. 27, 28 nQB1, QB1 Output Bank B differential clock output pair. CML interface levels. 30, 31 nQA1, QA1 Output Bank A differential clock output pair. CML interface levels.

REVISION B 07/20/15 3 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Table 3A. PLL Reference Clock Select Function Table NOTE: REF_SEL is an asynchronous control. Table 3B. FSELA[1:0] Output Divider Select Function Table NOTE: FSELA[1:0] are asynchronous controls. Using 25MHz input reference. Table 3C. FSELB[1:0] Output Divider Select Function Table NOTE: FSELB[1:0] are asynchronous controls. Using 25MHz input reference. Input OperationREF_SEL 0 (default) The crystal interface is the selected reference clock. 1 The REF_CLK input is the selected reference clock. Input Operation Output FrequencyFSELA1 FSELA0 0 (default) 0 (default) ÷ 2 312.5MHz 0 1 ÷ 4 156.25MHz 10 ÷ 5 1 2 5 M H z 11 ÷ 1 0 6 2 . 5 M H z Input Operation Output FrequencyFSELB1 FSELB0 0 (default) 0 (default) ÷ 2 312.5MHz 0 1 ÷ 4 156.25MHz 10 ÷ 5 1 2 5 M H z 11 ÷ 1 0 6 2 . 5 M H z

REVISION B 07/20/15 4 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Table 3D. PLL nBYPASS Function Table NOTE: nBYPASS is an asynchronous control. Table 3E. Output Enable Function Table NOTE: nOEA is an asynchronous control. Table 3F. Output Enable Function Table NOTE: nOEB is an asynchronous control. Input OperationnBYPASS 0 PLL is bypassed. The reference frequency fREF is divided by the selected output divider. AC specifications do not apply in PLL bypass mode. 1 (default) PLL is enabled. The reference frequency fREF is multiplied by the selected feedback divider and then divided by the selected output divider. Input OperationnOEA 0 (default) QA[1:0], nQA[ 1:0] Outputs enabled. 1 QA[1:0], nQA[1:0] Outputs disabled (high-impedance). Input OperationnOEB 0 (default) QB[1:0], nQB[ 1:0] Outputs enabled. 1 QB[1:0], nQB[1:0] Outputs disabled (high-impedance).

REVISION B 07/20/15 5 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 43.4°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.12 3.3 VDD V IDD Power Supply Current 71 89 mA IDDA Analog Supply Current 9 12 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage VDD – 0.11 2.5 VDD V IDD Power Supply Current 68 84 mA IDDA Analog Supply Current 8 11 mA

NOTE 1: Outputs are terminated with 50 to VDD. Table 5. Crystal Characteristics

Table 6. AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C has been reached under these conditions. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 5: Please refer to the phase noise plots. NOTE 6: Data was taken with both outputs at the same frequency.

REVISION B 07/20/15 8 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Typical Phase Noise at 125MHz Noise Power (dBc/Hz) Offset Frequency (Hz)

REVISION B 07/20/15 9 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Typical Phase Noise at 156.25MHz Noise Power (dBc/Hz) Offset Frequency (Hz)

REVISION B 07/20/15 10 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Parameter Measurement Information 3.3V CML Output Load Test Circuit Bank Skew Output Skew 2.5V CML Output Load Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx Power Supply GND VDD -3.3V ± 5% CML Driver VDDA tsk(b) QX0 nQX0 QX1 nQX1 Where X = A or B Qx nQx Qy nQy SCOPE Qx nQx Power Supply GND VDD -2.5V ± 5% CML Driver VDDA tPW tPERIOD tPW tPERIOD odc = x 100% nQA[0,1], nQB[0,1] QA[0,1], QB[0,1]

REVISION B 07/20/15 11 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Parameter Measurement Information, continued Output Rise/Fall Time Differential Output Voltage Swing nQA[0,1], nQB[0,1] QA[0,1], QB[0,1] 20% 80% 80% 20% tR tF nQA[0,1], nQB[0,1] QA[0,1], QB[0,1] VOUT VDIFF_OUT Differential Voltage Swing = 2 x Single-ended VIN

REVISION B 07/20/15 12 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. REF_CLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. Outputs: CML Outputs All unused CML outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

REVISION B 07/20/15 13 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50  applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface 100 100 RS 43 Ro ~ 7 Ohm Driver_LVCMOS Zo = 50 Ohm C1 0.1uF 3.3V 3.3V Crystal Input Interface XTAL_I N XTAL_OU T Crystal Input Interface XTAL_IN XTAL_OUT 0.1uF Zo = 50 Ohm LVPECL Zo = 50 Ohm VCC=3.3V

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

REVISION B 07/20/15 15 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR Figure 3 shows an example of 845264 application schematic. In this example, the device is operated at VDD = VDDA = 3.3V. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. A 12pF parallel resonant 25MHz crystal is used. For this device, the crystal load capacitors are required for proper operation. The load capacitance, C1 = C2 = 2pF , are recommended for frequency accuracy. Depending on the variation of the parasitic stray capacity of the printed circuit board traces between the crystal and the XTAL_IN and XTAL_OUT pins, the values of C1 and C2 might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used, but this will require adjusting C1 and C2. When designing the circuit board, return the capacitors to ground though a single point contact close to the package. Two Fox crystal options are shown in the schematic for design flexibility. The ePAD provides a low thermal impedance connection between the internal device and the PCB. It also provides an electrical connection to the die and must be connected to ground. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 845264 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.

Figure 3. 845264 Schematic Example corresponding VDD or VDDA pin.

25 MHz

This section provides information on power dissipation and junction temperature for the 845264. Equations and example calculations are also provided. The total power dissipation for the 845264 is the sum of the core power plus the power dissipation into the load. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation into the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below. Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection

1. Calculations and Equations.

Figure 4. CML Driver Circuit and Termination To calculate power dissipation per output pair into the load, use the following equations.

Table 8. JA vs. Air Flow Table for a 32 lead VFQFN

32 Lead VFQFN Package Outline and Package Dimensions

Table 9. Package Dimensions NOTE: The following package mechanical drawing is a generic package dimensions are in Table 9.

1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)

REVISION B 07/20/15 21 FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR

Ordering Information

Table 10. Ordering Information

FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR 22 REVISION B 07/20/15 Rev Table Page Description of Change Date B 16 Updated schematic with IDT crystal recommendation. Deleted prefix/suffix from part number throughout the datasheet. Updated header/footer. 7/20/15

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