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Technical content

Features

  • Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz and 312.5MHz
  • Four differential CML clock output pairs
  • 25MHz reference clock (selectable internal crystal oscillator and external LVCMOS clock)
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.405ps (typical) Offset Noise Power
  • LVCMOS interface levels for the control inputs
  • Full 3.3V and 2.5V supply voltage
  • Available in lead-free (RoHS 6) 32 VFQFN package
  • -40°C to 85°C ambient operating temperature
  • Replacement part: 843002AYLF 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nQ0 VDD nOE nc nc nc nc nQ3 REF_SEL FSEL1 FSEL0 nc VDD nc nc VDDA nBYPASS REF_CLK GND XTAL_OUT XTAL_IN nc nQ1 GND nQ2 FBSEL nc nc Block Diagram VCO 490-680 MHz nQ0 nQ1 nQ2 nQ3 Phase Detector ÷20, ÷25 (default) 1fREF OSC XTAL_IN XTAL_OUT REF_CLK REF_SEL FBSEL nBYPASS FSEL[1:0] nOE 1Pulldown Pulldown Pulldown Pullup Pulldown Pulldown ÷2 (default), ÷4, ÷5, ÷10 Pin Assignment 845254 32 lead VFQFN 5.0mm x 5.0mm x 0.925mm package body K Package Top View

845254 REVISION B 08/25/15 2 ©2015 Integrated Device Technology, Inc.

845254 Data Sheet FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR

Table 1. Pin Descriptions NOTE: Pulldown and pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ0, Q0 Output Differential clock output pair. CML interface levels. 3, 18 V DD Power Core supply pins. 4 nOE Input Pulldown Output enable pin. See Table 3E for function. LVCMOS/LVTTL interface levels. 17, 19, 25, 32 nc Unused Do not connect. 10 V DDA Power Analog supply pin. 11 nBYPASS Input Pullup PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels. 12 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 13, 29 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. FSEL1 Input Pulldown Output frequency divider select enable pins. See Table 3C for function. LVCMOS/LVTTL interface levels. 22 REF_SEL Input Pulldown PLL reference clock select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 23, 24 Q3, nQ3 Output Differential clock output pair. CML interface levels. 26 FBSEL Input Pulldown PLL feedback divider select pin. See Table 3B for function. LVCMOS/LVTTL interface levels. 27, 28 nQ2, Q2 Output Differential clock output pair. CML interface levels. 30, 31 nQ1, Q1 Output Differential clock output pair. CML interface levels.

845254 REVISION B 08/25/15 3 ©2015 Integrated Device Technology, Inc. Table 3A. PLL Reference Clock Select Function Table NOTE: REF_SEL is an asynchronous control. Table 3B. PLL Feedback Select Function Table NOTE: FBSEL is an asynchronous control. Table 3C. Output Divider Select Function Table NOTE: FSEL[1:0] are asynchronous controls. Table 3D. PLL nBYPASS Function Table NOTE: nBYPASS is an asynchronous control. Table 3E. Output Enable Function Table NOTE: nOE is an asynchronous control. Input OperationREF_SEL 0 (default) The crystal interface is the selected reference clock. 1 The REF_CLK input is the selected reference clock. Input OperationFBSEL 0 (default) f VCO = fREF * 25 1f VCO = fREF * 20 Input Operation Output Frequency fOUT with fREF = 25MHz FSEL1 FSEL0 FBSEL = 0 FBSEL = 1 0 (default) 0 (default) f OUT = fVCO ÷ 2 312.5MHz 250MHz 01 f OUT = fVCO ÷ 4 156.25MHz 125MHz 10 f OUT = fVCO ÷ 5 125MHz 100MHz 11 f OUT = fVCO ÷ 10 62.5MHz 50MHz Input OperationnBYPASS 0 PLL is bypassed. The reference frequency fREF is divided by the selected output divider. AC specifications do not apply in PLL bypass mode. 1 (default) PLL is enabled. The reference frequency fREF is multiplied by the selected feedback divider and then divided by the selected output divider. Input OperationnOE 0 (default) Outputs enabled. 1 Outputs disabled (high-impedance).

845254 REVISION B 08/25/15 4 ©2015 Integrated Device Technology, Inc. NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 43.4°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V IDD Power Supply Current 88 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.11 2.5 V DD V IDD Power Supply Current 84 mA IDDA Analog Supply Current 11 mA

845254 REVISION B 08/25/15 5 ©2015 Integrated Device Technology, Inc. Table 5. Crystal Characteristics

845254 REVISION B 08/25/15 6 ©2015 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: Characterized using an 18pF, 25MHz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Please refer to the phase noise plots.

845254 REVISION B 08/25/15 7 ©2015 Integrated Device Technology, Inc. Typical Phase Noise at 125MHz (3.3V) Noise Power dBc Hz Offset Frequency (Hz)

845254 REVISION B 08/25/15 8 ©2015 Integrated Device Technology, Inc. Typical Phase Noise at 156.25MHz (3.3V) Noise Power dBc Hz Offset Frequency (Hz)

845254 REVISION B 08/25/15 9 ©2015 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V CML Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V CML Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx Power Supply GND VDD -3.3V ± 5% CML Driver 20% 80% 80% 20% tR tF VOUT nQ[0:3] Q[0:3] SCOPE Qx nQx Power Supply GND VDD -2.5V ± 5% CML Driver Qx nQx Qy nQy tPW tPERIOD tPW tPERIOD odc = x 100% nQ[0:3] Q[0:3]

845254 REVISION B 08/25/15 10 ©2015 Integrated Device Technology, Inc. Figure 1. Power Supply Filtering resistance is not required but can be added for additional protection. protection, a 1k resistor can be tied from the REF_CLK to ground. should either be left floating or terminated.

845254 REVISION B 08/25/15 11 ©2015 Integrated Device Technology, Inc. chosen to minimize the ppm error. Figure 2. Crystal Input Interface device performance is guaranteed by using a quartz crystal.

845254 REVISION B 08/25/15 12 ©2015 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

845254 REVISION B 08/25/15 13 ©2015 Integrated Device Technology, Inc. Figure 5. 845254 Schematic Layout Example

845254 REVISION B 08/25/15 14 ©2015 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the 845254. Equations and example calculations are also provided. The total power dissipation for the 845254 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (88mA + 12mA) = 346.5mW
  • Power (outputs) MAX = 36.1mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 36.1mW = 144.4mW Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 144.4mW = 490.99mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.491W * 43.4°C/W = 106°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection

845254 REVISION B 08/25/15 15 ©2015 Integrated Device Technology, Inc.

  1. Calculations and Equations.

Figure 6. CML Driver Circuit and Termination

845254 REVISION B 08/25/15 16 ©2015 Integrated Device Technology, Inc. Table 8. JA vs. Air Flow Table for a 32 lead VFQFN

845254 REVISION B 08/25/15 17 ©2015 Integrated Device Technology, Inc. Table 9. Package Dimensions package dimensions are in Table 9.

  1. Type A: Chamfer on the paddle (near pin 1)
  2. Type C: Mouse bite on the paddle (near pin 1)

845254 REVISION B 08/25/15 18 ©2015 Integrated Device Technology, Inc.

Ordering Information

Table 10. Ordering Information

845254 REVISION B 08/25/15 19 ©2015 Integrated Device Technology, Inc. Rev Table Page Description of Change Date B 1 PDN #CQ-15-04 Product Discontinuance Notice – Last Time buy Expires on August 14, 2016. 08/25/15

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This produ ct is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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