845252AKILF | DigiCamel IC Datasheet

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ICS845252I IDT | Alldatasheet

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PDF pages: 17

Technical content

Features

Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz and 312.5MHz
Two differential CML clock output pairs
Crystal interface designed for 25MHz, 18pF parallel resonant crystal
RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 400fs (typical), 3.3V Offset Noise Power
LVCMOS interface levels for the control inputs
Full 3.3V and 2.5V supply voltage
Available in lead-free (RoHS 6) 32 VFQFN package
-40°C to 85°C ambient operating temperature HiPerClockS™ ICS Block Diagram VCO 490-680 MHz nQ0 nQ1 OSC XTAL_IN XTAL_OUT REF_CLK REF_SEL FBSEL nBYPASS FSEL1:0 nOE Phase Detector ÷20, ÷25 (default) ÷2 (default), ÷4, ÷5, ÷10 1fREF Pulldown Pulldown Pulldown Pullup Pulldown, Pulldown Pulldown Pin Assignment ICS845252I 32 lead VFQFN 5.0mm x 5.0mm x 0.925mm package body K Package Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nQ0 VDD nOE nc nc nc nc nc nc REF_SEL FSEL1 FSEL0 nc VDD nc nc VDDA nBYPASS REF_CLK GND XTAL_OUT XTAL_IN nc nc nc GND nQ1 FBSEL nc nc

ICS845252AKI REVISION A SEPTEMBER 30, 2009 2 ©2009 Integr ated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ0, Q0 Output Differential clock output pair. CML interface levels. 3, 18 V DD Power Core supply pins. 4n O E I n p u t P u l l d o w n Output enable pin. See Table 3E for function. LVCMOS/LVTTL interface levels. 10 V DDA Power Analog supply pin. 11 nBYPASS Input Pullup PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels. 12 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 13, 29 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 20, 21 FSEL0, FSEL1 Input Pulldown Output frequency divider select enable pins. See Table 3C for function. LVCMOS/LVTTL interface levels. 22 REF_SEL Input Pulldown PLL reference clock select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 26 FBSEL Input Pulldown PLL feedback divider select pin. See Table 3B for function. LVCMOS/LVTTL interface levels. 27, 28 nQ1, Q1 Output Differential clock output pair. CML interface levels.

ICS845252AKI REVISION A SEPTEMBER 30, 2009 3 ©2009 Integr ated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Function Tables Table 3A. PLL Reference Clock Select Function Table NOTE: REF_SEL is an asynchronous control. Table 3B. PLL Feedback Select Function Table NOTE: FBSEL is an asynchronous control. Table 3C. Output Divider Select Function Table NOTE: FSEL[1:0] are asynchronous controls. Table 3D. PLL nBYPASS Function Table NOTE: nBYPASS is an asynchronous control. Table 3E. Output Enable Function Table NOTE: nOE is an asynchronous control. Input OperationREF_SEL 0 (default) The crystal interface is the selected. 1 The REF_CLK input is the selected. Input OperationFBSEL 0 (default) f VCO = fREF * 25 1f VCO = fREF * 20 Input Operation Output Frequency fOUT with fREF = 25MHz FSEL1 FSEL0 FBSEL = 0 FBSEL = 1 0 (default) 0 (default) f OUT = fVCO ÷ 2 312.5MHz 250MHz 01 f OUT = fVCO ÷ 4 156.25MHz 125MHz 10 f OUT = fVCO ÷ 5 125MHz 100MHz 11 f OUT = fVCO ÷ 10 62.5MHz 50MHz Input OperationnBYPASS 0 PLL is bypassed. The reference frequency fREF is divided by the selected output divider. AC specifications do not apply in PLL bypass mode. 1 (default) PLL is enabled. The reference frequency fREF is multiplied by the selected feedback divider and then divided by the selected output divider. Input OperationnOE 0 (default) Outputs enabled. 1 Outputs disabled (high-impedance).

ICS845252AKI REVISION A SEPTEMBER 30, 2009 4 ©2009 Integr ated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 43.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V IDD Power Supply Current 88 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.11 2.5 V DD V IDD Power Supply Current 84 mA IDDA Analog Supply Current 11 mA

ICS845252AKI REVISION A SEPTEMBER 30, 2009 6 ©2009 Integr ated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR AC Characteristics Table 6A. AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: fREF = 25 MHz. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Please refer to the phase noise plots. Table 6B. AC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C For NOTES see Table 6A above. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency; NOTE 1 FBSEL = 0, FSEL[1:0] = 00 312.5 MHz FBSEL = 0, FSEL[1:0] = 01 156.25 MHz FBSEL = 0, FSEL[1:0] = 10 125 MHz FBSEL = 0, FSEL[1:0] = 11 62.5 MHz FBSEL = 1, FSEL[1:0] = 00 250 MHz FBSEL = 1, FSEL[1:0] = 01 125 MHz FBSEL = 1, FSEL[1:0] = 10 100 MHz FBSEL = 1, FSEL[1:0] = 11 50 MHz tsk(o) Output Skew; NOTE 1, 2, 3 60 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 4 FSEL = 0, 125MHz, Integration Range: 1.875MHz – 20MHz 400 fs FSEL = 0, 156.25MHz, Integration Range: 1.875MHz – 20MHz 408 fs t R / tF Output Rise/Fall Time 20% to 80% 300 850 ps odc Output Duty Cycle FBSEL[1:0] ≠ 10 48 52 % FBSEL[1:0] = 10 46 54 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency; NOTE 1 FBSEL = 0, FSEL[1:0] = 00 312.5 MHz FBSEL = 0, FSEL[1:0] = 01 156.25 MHz FBSEL = 0, FSEL[1:0] = 10 125 MHz FBSEL = 0, FSEL[1:0] = 11 62.5 MHz FBSEL = 1, FSEL[1:0] = 00 250 MHz FBSEL = 1, FSEL[1:0] = 01 125 MHz FBSEL = 1, FSEL[1:0] = 10 100 MHz FBSEL = 1, FSEL[1:0] = 11 50 MHz tsk(o) Output Skew; NOTE 1, 2, 3 60 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 4 FSEL = 0, 125MHz, Integration Range: 1.875MHz – 20MHz 406 fs FSEL = 0, 156.25MHz, Integration Range: 1.875MHz – 20MHz 441 fs t R / tF Output Rise/Fall Time 20% to 80% 300 850 ps odc Output Duty Cycle FBSEL[1:0] ≠ 10 48 52 % FBSEL[1:0] = 10 46 54 %

ICS845252AKI REVISION A SEPTEMBER 30, 2009 7 ©2009 Integr ated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Typical Phase Noise at 125MHz (3.3V) Noise Power dBc Hz Offset Frequency (Hz)

ICS845252AKI REVISION A SEPTEMBER 30, 2009 8 ©2009 Integr ated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Typical Phase Noise at 125MHz (2.5V) Noise Power dBc Hz Offset Frequency (Hz)

ICS845252AKI REVISION A SEPTEMBER 30, 2009 9 ©2009 Integr ated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Parameter Measurement Information 3.3V CML Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V CML Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period SCOPE Qx Power Supply GND VDD -3.3V ± 5% CML Driver Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Offset Frequency Markers Noise Power nQ0, nQ1 Q0, Q1 20% 80% 80% 20% tR tF VSWING SCOPE Qx Power Supply GND V DD -2.5V ± 5% CML Driver tsk(o) Qx nQx Qy nQy tPW tPERIOD tPW tPERIOD odc = x 100% nQ0, nQ1 Q0, Q1

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS845252I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering resistance is not required but can be added for additional protection. protection, a 1kΩ resistor can be tied from the REF_CLK to ground. should either be left floating or terminated.

ICS845252AKI REVISION A SEPTEMBER 30, 2009 12 ©2009 Integrated De vice Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS845252AKI REVISION A SEPTEMBER 30, 2009 13 ©2009 Integrated De vice Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS845252I. Equations and example calculations are also provided. The total power dissipation for the ICS845252I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. 125°C ensures that the bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

Calculations and Equations.

Figure 5. CML Driver (without built-in 50Ω pullup) Circuit and Termination

ICS845252AKI REVISION A SEPTEMBER 30, 2009 15 ©2009 Integrated De vice Technology, Inc. Table 8. θJA vs. Air Flow Table for a 32 VFQFN Table 9. Package Dimensions package dimensions are in Table 9.

ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The information contained herein is provided without re presentation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others . This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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Product Information

845252AKILF specifications and overview.

Summary

FemtoClock??Crystal-to-CML Clock Generator

Description

FemtoClock??Crystal-to-CML Clock Generator

Source title 845252AKILF Datasheet(PDF) - Integrated Device Technology

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