845252 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: epieczon
- PDF pages: 17
Technical content
Features
- Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz and 312.5MHz
- Two differential CML clock output pairs
- Crystal interface designed for 25MHz, 18pF parallel resonant crystal
- RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 400fs (typical), 3.3V Offset Noise Power
- LVCMOS interface levels for the control inputs
- Full 3.3V and 2.5V supply voltage
- Available in lead-free (RoHS 6) 32 VFQFN package
- -40°C to 85°C ambient operating temperature
- For functional replacement part use 8T49N241 Block Diagram VCO 490-680 MHz nQ0 nQ1 OSC XTAL_IN XTAL_OUT REF_CLK REF_SEL FBSEL nBYPASS FSEL1:0 nOE Phase Detector ÷20, ÷25 (default) ÷2 (default), ÷4, ÷5, ÷10 1fREF Pulldown Pulldown Pulldown Pullup Pulldown, Pulldown Pulldown Pin Assignment 845252 32 lead VFQFN 5.0mm x 5.0mm x 0.925mm package body K Package Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nQ0 VDD nOE nc nc nc nc nc nc REF_SEL FSEL1 FSEL0 nc VDD nc nc VDDA nBYPASS REF_CLK GND XTAL_OUT XTAL_IN nc nc nc GND nQ1 FBSEL nc nc 845252 Datasheet FemtoClock® Crystal-to-CML Clock Generator
845252 Datasheet
Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ0, Q0 Output Differential clock output pair. CML interface levels. 3, 18 V DD Power Core supply pins. 4 nOE Input Pulldown Output enable pin. See Table 3E for function. LVCMOS/LVTTL interface levels. 10 V DDA Power Analog supply pin. 11 nBYPASS Input Pullup PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels. 12 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 13, 29 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 20, 21 FSEL0, FSEL1 Input Pulldown Output frequency divider select enable pins. See Table 3C for function. LVCMOS/LVTTL interface levels. 22 REF_SEL Input Pulldown PLL reference clock select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 26 FBSEL Input Pulldown PLL feedback divider select pin. See Table 3B for function. LVCMOS/LVTTL interface levels. 27, 28 nQ1, Q1 Output Differential clock output pair. CML interface levels.
3©2016 Integrated Device Technology, Inc. Revision B, November 11, 2016 Table 3A. PLL Reference Clock Select Function Table NOTE: REF_SEL is an asynchronous control. Table 3B. PLL Feedback Select Function Table NOTE: FBSEL is an asynchronous control. Table 3C. Output Divider Select Function Table NOTE: FSEL[1:0] are asynchronous controls. Table 3D. PLL nBYPASS Function Table NOTE: nBYPASS is an asynchronous control. Table 3E. Output Enable Function Table NOTE: nOE is an asynchronous control. Input OperationREF_SEL 0 (default) The crystal interface is the selected. 1 The REF_CLK input is the selected. Input OperationFBSEL 0 (default) f VCO = fREF * 25 1f VCO = fREF * 20 Input Operation Output Frequency fOUT with fREF = 25MHz FSEL1 FSEL0 FBSEL = 0 FBSEL = 1 0 (default) 0 (default) f OUT = fVCO ÷ 2 312.5MHz 250MHz 01 f OUT = fVCO ÷ 4 156.25MHz 125MHz 10 f OUT = fVCO ÷ 5 125MHz 100MHz 11 f OUT = fVCO ÷ 10 62.5MHz 50MHz Input OperationnBYPASS 0 PLL is bypassed. The reference frequency fREF is divided by the selected output divider. AC specifications do not apply in PLL bypass mode. 1 (default) PLL is enabled. The reference frequency fREF is multiplied by the selected feedback divider and then divided by the selected output divider. Input OperationnOE 0 (default) Outputs enabled. 1 Outputs disabled (high-impedance).
4©2016 Integrated Device Technology, Inc. Revision B, November 11, 2016 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 43.4°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V IDD Power Supply Current 88 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.11 2.5 V DD V IDD Power Supply Current 84 mA IDDA Analog Supply Current 11 mA
Table 5. Crystal Characteristics
6©2016 Integrated Device Technology, Inc. Revision B, November 11, 2016 Table 6A. AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: fREF = 25 MHz. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Please refer to the phase noise plots. Table 6B. AC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C For NOTES see Table 6A above. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency; NOTE 1 FBSEL = 0, FSEL[1:0] = 00 312.5 MHz FBSEL = 0, FSEL[1:0] = 01 156.25 MHz FBSEL = 0, FSEL[1:0] = 10 125 MHz FBSEL = 0, FSEL[1:0] = 11 62.5 MHz FBSEL = 1, FSEL[1:0] = 00 250 MHz FBSEL = 1, FSEL[1:0] = 01 125 MHz FBSEL = 1, FSEL[1:0] = 10 100 MHz FBSEL = 1, FSEL[1:0] = 11 50 MHz tsk(o) Output Skew; NOTE 1, 2, 3 60 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 4 FSEL = 0, 125MHz, Integration Range: 1.875MHz – 20MHz 400 fs FSEL = 0, 156.25MHz, Integration Range: 1.875MHz – 20MHz 408 fs t R / tF Output Rise/Fall Time 20% to 80% 300 850 ps odc Output Duty Cycle FBSEL[1:0] 10 48 52 % FBSEL[1:0] = 10 46 54 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency; NOTE 1 FBSEL = 0, FSEL[1:0] = 00 312.5 MHz FBSEL = 0, FSEL[1:0] = 01 156.25 MHz FBSEL = 0, FSEL[1:0] = 10 125 MHz FBSEL = 0, FSEL[1:0] = 11 62.5 MHz FBSEL = 1, FSEL[1:0] = 00 250 MHz FBSEL = 1, FSEL[1:0] = 01 125 MHz FBSEL = 1, FSEL[1:0] = 10 100 MHz FBSEL = 1, FSEL[1:0] = 11 50 MHz tsk(o) Output Skew; NOTE 1, 2, 3 60 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 4 FSEL = 0, 125MHz, Integration Range: 1.875MHz – 20MHz 406 fs FSEL = 0, 156.25MHz, Integration Range: 1.875MHz – 20MHz 441 fs t R / tF Output Rise/Fall Time 20% to 80% 300 850 ps odc Output Duty Cycle FBSEL[1:0] 10 48 52 % FBSEL[1:0] = 10 46 54 %
7©2016 Integrated Device Technology, Inc. Revision B, November 11, 2016 Typical Phase Noise at 125MHz (3.3V) Noise Power dBc Hz Offset Frequency (Hz)
8©2016 Integrated Device Technology, Inc. Revision B, November 11, 2016 Typical Phase Noise at 125MHz (2.5V) Noise Power dBc Hz Offset Frequency (Hz)
9©2016 Integrated Device Technology, Inc. Revision B, November 11, 2016 Parameter Measurement Information 3.3V CML Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V CML Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period SCOPE Qx Power Supply GND VDD -3.3V ± 5% CML Driver nQ0, nQ1 Q0, Q1 20% 80% 80% 20% tR tF VSWING SCOPE Qx nQx Power Supply GND VDD -2.5V ± 5% CML Driver Qx nQx Qy nQy tPW tPERIOD tPW tPERIOD odc = x 100% nQ0, nQ1 Q0, Q1
10©2016 Integrated Device Technology, Inc. Revision B, November 11, 2016
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 845252 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering resistance is not required but can be added for additional protection. protection, a 1k resistor can be tied from the REF_CLK to ground. should either be left floating or terminated.
chosen to minimize the ppm error. Figure 2. Crystal Input Interface Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
and the inner edges of pad pattern for the leads to avoid any shorts. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
This section provides information on power dissipation and junction temperature for the 845252. Equations and example calculations are also provided. The total power dissipation for the 845252 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (88mA + 12mA) = 346.5mW
- Power (outputs) MAX = 35.76mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 35.76mW = 71.52mW Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 71.52mW = 418.02mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.418W * 43.4°C/W = 103°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
- Calculations and Equations.
Figure 5. CML Driver (without built-in 50 pullup) Circuit and Termination
Table 8. JA vs. Air Flow Table for a 32 VFQFN Table 9. Package Dimensions package dimensions are in Table 9.
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Table 10. Ordering Information A 1 Product Discontinuation Notice - Last time buy expires November 2, 2016. Obsolete datasheet per PDN# CQ-15-05. Ordering Information table - deleted Tape & Reel count and table note. Updated datasheet header/footer.
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