ICS845204 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Four differential spread spectrum clock outputs
  • Each output can be individually disabled by separate output-enable inputs
  • Crystal oscillator interface designed for 18pF , 25MHz parallel resonant crystal
  • Supports the following output frequencies: 25MHz, 100MHz, 125MHz or 250MHz
  • VCO range: 250MHz - 700MHz
  • Supports SSC downspread at 0.05% and -0.75%, centerspread at ±0.25% and no spread options
  • Cycle-to-cycle jitter: 50ps (maximum) design target
  • Period jitter, RMS: TBD
  • Full 3.3V output supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages The Advance Information presented herein represents a product that is developmental or prototype. The noted characteristics are design targets. Integrated Device Technologies, Inc. (IDT) reserves the right to change any circuitry or specifications without notice. HiPerClockS™ ICS Phase Detector VCO 250-700MHz Feedback Divider ÷20 Spread Spectrum Control OSC nQ0 OE0 nQ1 nQ2 nQ3 XTAL_IN XTAL_OUT SSC[1:0] FSEL[1:0] Pullup Pullup Pullup PullupDefault = 100MHz 25MHz Pullup:Pullup Pulldown:Pullup OE1 OE2 OE3 0 0 PLL Bypass 0 1 ÷5 1 0 ÷4 1 1 ÷2 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 OE0 VDD nQ3 VDDO nc FSEL0 nc nc nc GND nQ2 SSC1 nc GND FSEL1 SSC0 VDD OE3 XTAL_IN XTAL_OUT OE2 GND nQ0 GND OE1 VDDA nc nQ1 Pin Assignment ICS845204

32 Lead VFQFN

5mm x 5mm x 0.925mm package body K Package Top View Block Diagram

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 OE0 Input Pullup Output enable pin for Q0/nQ0 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. 2, 11 V DD Power Core supply pins. 3, 4 nQ3, Q3 Output Differential outp ut pair. M-LVDS interface levels. 5V DDO Power Output supply pin. 24, 27 nc Unused No connect. 7 FSEL0 Input Pullup Output frequency select pins. See Table 3A. LVCMOS/LVTTL interface levels. 9 FSEL1 Input Pulldown Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels. SSC1 Input Pullup Spread spectrum control pins. Se e Table 3B. LVCMOS/LVTTL interface levels. 12 OE3 Input Pullup Output enable pin for Q3/nQ3 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 15 OE2 Input Pullup Output enable pin for Q2/nQ2 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. 16, 17, 22, 30 GND Power Power supply ground. 20, 21 nQ2, Q2 Output Diffe rential output pair. M-LVDS interface levels. 25, 26 nQ1, Q1 Output Diffe rential output pair. M-LVDS interface levels. 28 V DDA Power Analog supply pin. 29 OE1 Input Pullup Output enable pin for Q1/nQ1 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. 31, 32 nQ0, Q0 Output Diffe rential output pair. M-LVDS interface levels.

CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM ADVANCE INFORMATION IDT™ / ICS™ M-LVDS CLOCK SYNTHESIZER 3 ICS845204AK SEPTEMBER 25, 2007 Function Tables Table 3A. F_SEL[1:0] Function Table Table 3B. SSC[1:0] Function Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Inputs Outputs FSEL1 FSEL0 Q[0:3]/nQ[0:3] 0 0 PLL Bypass (25MHz) 0 1 100MHz (default) 1 0 125MHz 1 1 250MHz Inputs Spread% SSC1 SSC0 0 0 Center ± -0.25 0 1 Down -0.5 1 0 Down -0.75 1 1 No Spread (default) Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 42.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – IDDA*10Ω 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current TBD mA IDDA Analog Supply Current TBD mA IDDO Power Supply Current TBD mA

Table 5. Crystal Characteristics

Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70° NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Only valid within the VCO operating range. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Spread Spectrum clocking enabled.

25 MHz

100 MHz

125 MHz

CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM ADVANCE INFORMATION IDT™ / ICS™ M-LVDS CLOCK SYNTHESIZER 6 ICS845204AK SEPTEMBER 25, 2007 Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Skew Output Rise/Fall Time Period Jitter Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND M-LVDS VDD, VDDO VDDA tsk(o) Qx nQx nQy Qy Clock Outputs 20% 80% 80% 20% tR tF VOD VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1

1000 Cycles

odc = x 100% nQ0:nQ3 Q0:Q3

CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM ADVANCE INFORMATION IDT™ / ICS™ M-LVDS CLOCK SYNTHESIZER 7 ICS845204AK SEPTEMBER 25, 2007 Parameter Measurement Information, continued Offset Voltage Setup Differential Output Voltage Setup

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS845204 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a 0.01µF bypass capacitor should be connected to each VDDA pin. Figure 1. Power Supply Filtering protection. A 1kΩ resistor can be used.

the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. Enhance Leadfame Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

a matched load termination of 100Ω across near the receiver input. used, it is recommended to terminate the unused outputs. Figure 5. Typical M-LVDS Driver Termination Table 7. θJA vs. Air Flow Table for a 32Lead VFQFN

page. The package dimensions are in Table 8 below. Table 8. Package Dimensions

CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM ADVANCE INFORMATION IDT™ / ICS™ M-LVDS CLOCK SYNTHESIZER 12 ICS845204AK SEPTEMBER 25, 2007

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT product for use in life support devices or critical medical instruments.

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