844S42I

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Technical content

Features

• Programmable frequency synthesis optimized for instrumentation, networking and computing applications
• 81MHz to 2592MHz synthesized clock output signal
• Two differential, universal LVDS or LVPECL compatible high-frequency outputs
• Output frequency programmable through 2-wire I2C bus or parallel interface
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS/LVTTL compatible reference clock input
• Clock stop and output enable functionality
• PLL lock indicator output (LVCMOS/LVTTL)
• LVCMOS/LVTTL compatible control inputs
• Fully integrated PLL
• SiGe Technology
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in a lead-free (RoHS 6) compliant package Pin Assignment 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND nc nBYPASS nc VDD REF_CLK GND VDD REF_SEL XTAL_IN XTAL_OUT nMR LOCK_DT LEV_SEL nc VDDOA VDDOA QA nQA GND nc GND GND GND QB nQB VDDOB VDDOB VDD GND GND P NA0 NA1 NA2 NB0 NB1 NB2 SDA SCL nPLOAD VDD 484950515253545556 47 46 45 44 43 nc ADR1 ADR0 VDDA ICS844S42I 56-Lead VFQFN 8mm x 8mm x 0.925mm package body K Package Top View 844S42I Data Sheet Dual Output RF Frequency Synthesizer

2©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Block Diagram OSC PLL ÷NB ÷NA fREF fVCO fQA fQB REF_CLK XTAL_IN XTAL_OUT REF_SEL SDA SCL ADR[1:0] nPLOAD M[9:0] NA[2:0] NB[2:0] P LEV_SEL nBYPASS nMR QA QB LOCK_DT PLL Configuration Registers I2C Control fPD

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 35, 36, 37 GND Power Power supply ground. 2, 4, 29, 42, 43 nc Unused Do not connect. 3 nBYPASS Input Pulldown PLL bypass. LV CMOS/LVTTL interface levels. 5, 14, 15, 28 V DD Power Digital power supply pins. 6 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 8 REF_SEL Input Pullup Reference select pi n. LVCMOS/LVTTL interface levels. XTAL_OUT Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 2C, output dividers and the LOCK_DT. LVCMOS/LVTTL interface levels. 12 LOCK_DT Output Lock detect output. LVCMOS/LVTTL interface levels. 13 LEV_SEL Input Pulldown Output level select (LVDS and LVPECL). LVCMOS/LVTTL interface levels. 17 P Input Pullup Parallel configuration of PLL pre-divider. LVCMOS/LVTTL interface levels. 18, 19, 20 NA0, NA1, NA2 Input Pulldown Parallel configuration of QA output dividers. LVCMOS/LVTTL interface levels. 21, 22, 23 NB0, NB1, NB2 Input Pulldown Parallel configuration of QB output dividers. LVCMOS/LVTTL interface levels. 24 SDA I/O Pullup I 2C data input/output pin.LVCMOS/LVTTL interface levels. 25 SCL I/O Pullup I 2C clock.LVCMOS/LVTTL interface levels. 26 nPLOAD Input Pulldown Selects the programming interface. LVCMOS/LVTTL interface levels. 30, 31 V DDOB Power Bank B output power supply pins. 32, 33 nQB, QB Output QB differential clock output pair. LVPECL or LVDS interface levels. 38, 39 nQA, QA Output QA differential clock output pair. LVPECL or LVDS interface levels. DDOA Power Bank A output power supply pins. Parallel configuration of PLL feedback dividers. 54, 55 ADR0, ADR1 Input Pulldown Bits 2 and 1 of the device I 2C address. LVCMOS/LVTTL interface levels. 56 V DDA Power Internal PLL power supply pin.

Table 2. Pin Characteristics the core logic and output drivers to minimize noise induced jitter. is indicated by the LVCMOS-compatible LOCK_DT output.

5©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Device Configuration The ICS844S42I supports an output frequency range of 81MHz to 2592MHz. The output frequency fOUT is a function of the reference frequency fREF and the three internal PLL dividers P, M, and N. fOUT can be represented by this formula: fOUT = (fREF ÷ P) · M ÷ (NA, NB) The M, N and P dividers require a configuration by the user to achieve the desired output frequency. The output dividers NA, NB determine the achievable output frequency range (see Table 3A). The PLL feedback-divider M is the frequency multiplication factor and the main variable for frequency synthesis. For a given reference frequency f REF, the PLL feedback-divider M must be configured to match the specified VCO frequency range in order to achieve a valid PLL configuration: fVCO = (fREF ÷ P) · M and 1296MHz  fVCO  2592MHz The output frequency may be changed at any time by changing the value of the PLL feedback divider M. The smallest possible output frequency change is the synthesizer granularity G (difference in fOUT when incrementing or decrementing M). At a given reference frequency, G is a function of the PLL pre-divider P and post-divider G = f REF ÷ (P · NA, NB) The purpose of the PLL pre-divider P is to situate the PLL into the specified VCO frequency range fVCO (in combination with M). For a given output frequency, P = ÷4 results in a smaller output frequency granularity G, P = ÷2 results a larger output frequency granularity G and also decreases the PLL bandwidth compared to the P = ÷4 setting. The following example illustrates the output frequency range of the 844S42I using a 16MHz reference frequency. Table 3A. Device Configuration Table for fREF = 16MHz) Output Frequency (MHz) NA, NB M P G (MHz) 1296 – 2592 1 324 – 648 4 4 162 – 324 2 8 648 – 1296 2 324 – 648 4 2 162 – 324 2 4 432 – 864 3 324 – 648 4 1.33 162 – 324 2 2.66 324 – 648 4 324 – 648 4 1 162 – 324 2 2 216 – 432 6 324 – 648 4 0.66 162 – 324 2 1.33 162 – 324 8 324 – 648 4 0.5 162 – 324 2 1 81 – 162 16 324 – 648 4 0.25 162 – 324 2 0.5

6©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Example Output Frequency Configuration If a single reference frequency of 16MHz is available, an output frequency at QA of 2500MHz and a small frequency granularity is desired, the following steps would be taken to identify the appropriate P, M, and N configuration: 1. Use Table 3A to select the output divider, NA, that matches the desired output frequency or frequency range. According to Table 3A a target output frequency of 2500MHz falls in the f OUT range of 1296MHz to 2592MHz and requires to set NA = 1. 2. Calculate the VCO frequency fVCO = fOUT · NA, which is 2500MHz in this example. 3. Determine the PLL feedback divider: M = fVCO ÷ P. The smallest possible output granularity in this example calculation is 4MHz (set P = 4). M calculates to a value of 2500MHz ÷ 4 = 625MHz. 4. Configure the 844S42I with the obtained settings:  M[9:0] = 1001110001b (binary number for M = 625)  NA[2:0] = 000 (÷1 divider, see Table 3C)  P = 1 (÷4 divider, see Table 3B)  NB[2:0] = 111 will stop (disable) the QB output 5. Use either parallel or serial interface to apply the setting. The I 2C configuration byte for this examples are: 0x00 = 01110001b, 0x01 = 10111000b and 0x02 = 10000000b. See Table 3H for a register map. PLL Divider Configuration Table 3B. Pre-Divider (P) Table Table 3C. Post-Divider (Nx) Table P Pre-Divider P Operation 02 f PD = fREF ÷ 2 1 (default) 4 f PD = fREF ÷ 4 NA, NB Post-Divider NA, NB Operation210 0 (default) 0 (default) 0 (default) 1 f QA, fQB = fVCO ÷ 1 001 2 f QA, fQB = fVCO ÷ 2 010 3 f QA, fQB = fVCO ÷ 3 011 6 f QA, fQB = fVCO ÷ 6 100 4 f QA, fQB = fVCO ÷ 4 101 8 f QA, fQB = fVCO ÷ 8 1101 6 f QA, fQB = fVCO ÷ 16 1 1 1 N/A Output stopped in logic low state

7©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Programming the 844S42I The 844S42I has a parallel and a serial configuration interface. The purpose of the parallel interface is to directly configure the PLL dividers through hardware pins without the overhead of a serial protocol. At device startup, the device always obtains an initial PLL frequency configuration through the parallel interface. The parallel interface does not support reading the PLL configuration. The serial interface is I 2C compatible. It allows reading and writing devices settings by accessing internal device registers. The serial interface is designed for host-controller access to the synthesizer frequency settings, for instance, in frequency-margining applications. Using the Parallel Interface The parallel interface supports write-access to the PLL frequency setting directly through 17 configuration pins (P, M[9:0], NA[2:0], and NB[2:0]). The parallel interface must be enabled by setting nPLOAD to logic low level. During nPLOAD = 0, any change of the logical state of the P, M[9:0], NA[2:0] and NB[2:0] pins will immediately affect the internal PLL divider settings, resulting in a change of the internal VCO frequency and the output frequency. The parallel interface mode disables the I 2C write-access to the internal registers; however, I2C read-access to the internal configuration registers is enabled. Upon startup, when the device reset signal is released (rising edge of the nMR signal), the device reads its startup configuration through the parallel interface and independent of the state of nPLOAD. It is recommended to provide a valid PLL configuration for startup. If the parallel interface pins are left open, a default PLL configuration will be loaded. After the low-to-high transition of nPLOAD, the configuration pins have no more effect and the configuration registers are made accessible through the serial interface. Table 3D. PLL Feedback Divider (M) Configuration Table Table 3E. PLL Post-Divider (NA) Configuration Table Table 3F. PLL Post-Divider (NB) Configuration Table Table 3G. PLL Pre-Divider (P) Configuration Table M B i t s 9876543210 Pin M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 D e f a u l t 1001110001 NA Bits 2 1 0 Pin NA2 NA1 NA0 Default 0 0 0 NB Bits 2 1 0 Pin NB2 NB1 NB0 Default 0 0 0 P Pin P Default 1

8©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Using the I2C Interface nPLOAD = 1 enables the programming and monitoring of the internal registers through the I2C interface. Device register access (write and read) is possible through the 2-wire interface using SDA (configuration data) and SCL (configuration clock) signals. The 844S42I acts as a slave device at the I2C bus. For further information on I2C it is recommended to refer to the I2C bus specification (version 2.1). nPLOAD = 0 disables the I2C-write-access to the configuration registers and any data written into the register is ignored. However, the 844S42I is still visible at the I2C interface and I2C transfers are acknowledged by the device. Read-access to the internal registers during nPLOAD = 0 (parallel programming mode) is supported. Note that the device automatically obtains a configuration using the parallel interface upon the release of the device reset (rising edge of nMR) and independent on the state of nPLOAD. Changing the state of the nPLOAD input is not supported when the device performs any transactions on the I 2C interface. Programming Model and Register Set The synthesizer contains three fully accessible configuration registers (0x00 through 0x02). Programming the synthesizer frequency through the I2C interface is a one step process at which all registers are written at once by a single I2C transaction. The PLL frequency is affected as a result of the completion of the entire three register file write access at the end of writing byte 0x02. The configuration registers are read as a single I2C transaction. All registers are read back-to-back. Note that the synthesizer does not check any boundary conditions such as the VCO frequency range. Writing the PLL registers could result in invalid VCO frequencies (VCO frequency beyond lock range). Register Map It is always required to configure the entire 844S42I register file (0x00, 0x01, 0x02), addressing single register bytes is not supported. Writing any information to the bits 2, 1 and 0 in register 0x02 is ignored. These bits indicate information updated by the synthesizer (bit 2 is the PLL lock status, bits 1 and 0 are copies of the ADR[1:0] pin status). Table 3H. Register File Table I2C Register Access in Parallel Mode The 844S42I supports the configuration of the synthesizer through the parallel interface (nPLOAD = 0) and serial interface (nPLOAD = 1). Register contents and the divider configurations are not changed when the user switches from parallel mode to serial mode. However, when switching from serial mode to parallel mode, the PLL dividers immediately reflect the logical state of the hardware pins M[9:0], NA[2:0], NB[2:0], and P. Applications using the parallel interface to obtain a PLL configuration can use the serial interface to verify the divider settings. In parallel mode (nPLOAD = 0), the 844S42I allows read-access to the registers through I 2C (if nPLOAD = 0), the current PLL configuration is stored in the registers. After changing from parallel to serial mode (nPLOAD = 1), the last PLL configuration is still stored in the registers. The user now has full write and read access to both configuration registers through the I2C bus and can change the configuration at any time. R e g i s t e r A d d r e s s 76543210 A ccess 0x00H M7 M6 M5 M4 M3 M2 M1 M0 R/W D e f a u l t 01110001 0x01H M9 M8 NA2 NA1 NA0 NB2 NB1 NB0 R/W D e f a u l t 10000000 0x02H P RES RES RES RES LOCK ADR1 ADR0 R/W D e f a u l t 10000000

9©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Programming the I2C Interface Table 3I. I2C Slave Address Table The 844S42I acts as a slave device at the I2C bus. The register file is reset to its default values at power-up by an integrated power-on reset circuit or by applying an external device reset signal (nMR).The 7-bit I2C slave address of the 844S42I synthesizer is a combination of a 5-bit fixed addresses and two variable bits which are set by the hardware pins ADR[1:0]. Bit 0 of the 844S42I slave address is used by the bus controller to select either the read or write mode. ‘0’ indicates a transmission (I 2C-WRITE) to the 844S42I. “1” indicates a request for data (I2C-READ) from the synthesizer. The hardware pins ADR1 and ADR0 and should be individually set by the user to avoid address conflicts of multiple 844S42I devices on the same I bus. Each access to the I2C register file must read or write the entire four register bytes at one time. Each transfer starts with register 0x00H, followed by register 0x01H, until register 0x02H. Addressing individual bytes is not supported. The bytes will program internal part circuitry upon receipt of all three bytes and a given I2C bus <STOP> signal. Device Startup General Device Configuration: It is recommended to reset the 844S42I after the system powers up. The device acquires an initial PLL divider configuration through the parallel interface pins M[9:0], NA[2:0], NB[2:0] and P NOTE1 with the low-to-high transition of nMRNOTE2. PLL frequency lock is achieved within the specified lock time (tLOCK) and is indicated by an assertion of the LOCK_DT signal which completes the startup procedure. The output frequency can be reconfigured at any time through either the parallel or the serial interface. Starting-Up Using the Parallel Interface The simplest way to use the 844S42I is through the parallel interface. The serial interface pins (SDA, SDL, and ADR[1:0]) can be left open and nPLOAD is set to logic low. After the release of nMR and at any other time the PLL and output frequency configuration is directly set to through the M[9:0], NA[2:0], NB[2:0] and P pins. Table 3J. REF_SEL Configuration Table Table 3K. nBYPASS Configuration Table The nBYPASS control should be set to logic LOW for normal operation. nBYPASS = 1 enables the PLL bypass mode for factory test. In PLL bypass mode, the output frequency is equal to the input frequency divided by NA, NB and frequency multiplication is disabled. Table 3L. nMR Configuration Table The output type and output voltage levels of both outputs are configured through the configuration input LEV_SEL. LEV_SEL connected to logic high results in LVPECL output levels and LEV_SEL connected to logic low results in LVDS output levels of both QA and QB differential outputs. Table 3M. LEV_SEL Configuration Table Table 3N. LOCK_DT Configuration Table NOTE 1: The parallel interface pins M[9:0], NA[2:0], NB[2:0] and P may be left open (floating). In this case the initial PLL configuration will have the default setting of M = 625MHz, P = 1 (÷4), NA[2:0] = 000 (÷1), NB[2:0] = 000 (÷1), resulting in an internal VCO frequency of 2500MHz (fREF = 16MHz) and an output frequency of 2500MHz at both outputs. NOTE 2: The initial PLL configuration is independent on the selected programming mode (nPLOAD low or high). Bit 7 6 5 4 3 2 1 0 Value 1 0 1 1 0 ADR1 ADR0 R/W REF_SEL Operation

0 Selects REF_CLK input as reference frequency

1 (default) Selects the XTAL interface as reference frequency nBYPASS Operation 0 (default) fQA, fQB = ((fREF ÷ P) * M) ÷ NA, NB PLL operation 1 fQA, fQB = fREF ÷ NA, NB PLL is bypassed, AC specifications do not apply nMR Operation

0 The device is reset and the default settings are

loaded into the I2C file (low to high transition of nMR) 1 (default) Normal operation LEV_SEL Operation 0 (default) QA, QB outputs are LVDS compatible

1 QA, QB outputs are LVPECL compatible

LOCK_DT Operation

0 Device is not locked to the input reference clock

1 Device is locked to the input reference clock

10©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Refer to the Power Considerations section. In LVDS output mode, the IDD, IDDA and IDDO specifications apply. IDDO is the current through all VDDOA and VDDOB pins. In LVPECL mode, the IGND specification applies. IGND is the current through all GND pins. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, I O (LVDS) Continuos Current Surge Current Outputs, VO (LVCMOS) 50mA 100mA 10mA 15mA -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 31.4°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.23 3.3 V DD V VDDOA, VDDOB Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current LEV_SEL = 0 195 mA IDDA Analog Supply Current LEV_SEL = 0 23 mA IDDOA + IDDOB Output Supply Current LEV_SEL = 0 52 mA IGND Power Supply Current LEV_SEL = 1 275 mA

11©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4C. LVDS DC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to 85°C Table 4D. LVPECL DC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: Outputs termination with 50 to VDDOx – 2V. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2.2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current REF_CLK, nPLOAD, LEV_SEL, ADR[1:0], M2, M3, M7, M8, nBYPASS V DD = VIN = 3.465V 150 µA M0, M4, M5, M6, M9, P, nMR, SDA, SCL, REF_SEL VDD = VIN = 3.465V 10 µA IIL Input Low Current REF_CLK, nPLOAD, LEV_SEL, ADR[1:0], M2, M3, M7, M8, nBYPASS V DD = 3.465V, VIN = 0V -10 µA M0, M4, M5, M6, M9, P, nMR, SDA, SCL, REF_SEL V DD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage LOCK_DT I OH = -12mA 2.6 V VOL Output Low Voltage LOCK_DT I OL = 12mA 0.5 V Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VOD Differential Output Voltage LEV_SEL = 0 300 400 500 V VOD VOD Magnitude Change LEV_SEL = 0 50 mV VOS Offset Voltage LEV_SEL = 0 1.1 1.2 1.3 V VOS VOS Magnitude Change LEV_SEL = 0 50 mV Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 LEV_SEL = 1 V DDOx – 1.2 V DDOx – 0.8 V VOL Output Low Voltage; NOTE 1 LEV_SEL = 1 V DDOx – 2.0 V DDOx – 1.4 V VSWING Peak-to-Peak Output Voltage Swing LEV_SEL = 1 0.6 1 V

Table 5. Crystal Characteristics Table 6. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to +85°C has been reached under these conditions. differential crossing point. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Other output divider combinations may yield much greater output skews.

13©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit RMS Period Jitter Output Skew 3.3V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter LVPECL Output Rise/Fall Time 3.3V ±5% VDDA VDDOA, VDD, VDDOB VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nQx Qx nQy Qy SCOPE Qx nQx GND VDDA -1.3V±0.165V VDD, VDDOA, VDDOB, tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QA, QB nQA, nQB QA, QB nQA, nQB

14©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Parameter Measurement Information, continued LVDS Output Rise/Fall Time Offset Voltage Setup Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup 20% 80% 80% 20% tR tF VOD QA, QB nQA, nQB QA, QB nQA, nQB

15©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 844S42I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and VDDOB should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering for additional protection. A 1k  resistor can be used. we recommend that there is no trace attached.

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

19©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL out puts. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 6A. 3.3V LVPECL Output Termination Figu re 6B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

21©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Power Considerations – LVPECL Outputs This section provides information on power dissipation and junction temperature for the 844S42I, for all outputs that are configured to LVPECL (LEV_SEL = 1). Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 844S42I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  Power (core) MAX = VDD_MAX * IGND_MAX = 3.465V * 260mA = 900.9mW  Power (outputs) MAX = 36mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 36mW = 72mW Total Power_MAX (3.465V, with all outputs switching) = 800.9mW + 72mW = 972.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 31.4°C/W per Table 7A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7A. Thermal Resistance JA for 56 Lead VFQFN Forced Convection JA by Velocity Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 31.4°C/W 27.5°C/W 24.6°C/W

1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 8. Figure 8. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

23©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet Power Considerations – LVDS Outputs This section provides information on power dissipation and junction temperature for the 844S42I for all outputs that are configured to LVDS (LEV_SEL = 0). Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 844S42I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum current at 85°C is as follows: IDD_MAX = 185mA IDDA_MAX = 22mA IDDO_MAX = 50mA  Power (core) MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (185mA + 22mA) = 717.255mW  Power (output) MAX = VDDO_MAX * (IDDOA + IDDOB) = 3.465V * 50mA = 173.25mW Total Power_MAX = 717.255mW + 173.25mW = 890.505mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 31.4°C/W per Table 7B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.891W * 31.4°C/W = 113°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7B. Thermal Resistance JA for 56 Lead VFQFN, Forced Convection JA by Velocity Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 31.4°C/W 27.5°C/W 24.6°C/W

Table 8. JA vs. Air Flow Table for a 56 Lead VFQFN

Table 9. Package Dimensions package dimensions are in Table 9.

1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)

26©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet

Ordering Information

Table 10. Ordering Information

27©2016 Integrated Device Technology, Inc Revision A April 28, 2016 844S42I Data Sheet

Revision History

Revision Date Description of Change April 28, 2016 ▪ Removed ICS from part numbers where needed. ▪ Ordering Information - Remove quantity from Tape and Reel. Deleted LF note below table. ▪ Update data sheet headers and footers.

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