844S2416CKILF

844S2416I IDT | Alldatasheet

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FemtoClock® NG Crystal-to-Differential HCSL/LVCMOS Frequency Synthesizer 844S2416 Data Sheet ©2016 Integrated Device Technology, Inc Revision A April 29, 20161 GENERAL DESCRIPTION The 844S2416 is a 17 output, dual-PLL frequency synthesizer optimized to generate a variety of clocks for Ethernet, USB and other interfaces. Using a 25MHz 18pF parallel resonant crystal, the device will generate 24MHz, 25MHz, 100MHz and 200MHz clocks withmixed HCSL and LVCMOS/LVTTL levels. The 844S2416 is packaged in a 56-pin VFQFN package that is optimum for applications with space limitations.

FEATURES

• Two LVCMOS/LVTTL single-ended outputs at 24MHz Twelve LVCMOS/LVTTL single-ended outputs at 25MHz Two differential HCSL output pairs at 100MHz One differential HCSL output pair at 100MHz or 200MHz
• Crystal oscillator interface: 25MHz
• PLL1 – VCO: 2.4GHz
• PLL2 – VCO range: 1.8GHz - 2.2GHz ±10% frequency margining in 1.25% steps Selectable spread spectrum – downspread at -0.5%
• I C control interface with address confi guration pin and with default loading on release of active low reset
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package PIN ASSIGNMENT 56-Lead VFQFN 8mm x 8mm x 0.925mm package body K Package Top View

©2016 Integrated Device Technology, Inc Revision A April 29, 20162 BLOCK DIAGRAM OSC SCL IREF SDA ADDR nRESET XTAL_IN XTAL_OUT Pullup Pulldown Pullup Pulldown 25MHz Phase Detector LC VCO 2.4GHz ÷96 72 - 88 (80 default) Controlled by M4:M0 Spread Spectrum ÷25 Q15 nQ15 Q16 nQ16 HCSL - 100MHz Q12 nQ12 Q13 Q14 LVCMOS - 24MHz HCSL - 100MHz or 200MHz Q0, Q2, Q4, Q6, Q8, Q10 Q1, Q3, Q5, Q7, Q9, Q11 LVCMOS - 25MHz Phase Detector Ring VCO 1.8 – 2.2GHz ÷10, I2C Control Block PLL 1 PLL 2 Bypass Output Enable

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 2, 3 Q16, nQ16 Output Differential clock outputs. HCSL interface levels. 4, 5 Q15, nQ15 Output Differential clock outputs. HCSL interface levels. GND Power Power supply ground. XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input. for power sequencing. LVCMOS/LVTTL interface levels. 11 ADDR Input Pulldown Serial address select pin. LVCMOS/ LVTTL interface levels.

12 SDA I/O Pullup I

C serial data input. LVCMOS/ LVTTL interface levels.

13 SCL Input Pulldown I

C serial clock input. LVCMOS/ LVTTL interface levels. Power Output supply pins for LVCMOS/LVTTL outputs. Output Single-ended non-inverted clock outputs. LVCMOS/LVTTL interface levels. Single-ended inverted clock outputs. LVCMOS/LVTTL interface levels. 30, 31 Q12, nQ12 Output Differential clock outputs. HCSL interface levels.

33 IREF

Power Analog supply pin for PLL2. Power Analog supply pin for PLL1. Pullup and Pulldown refer to internal input resistors. See Table 5, Pin Characteristics, for typical values.

©2016 Integrated Device Technology, Inc Revision A April 29, 20164 The 844S2416 uses an industry standard I C interface to control the programming of the output enables of every output, the feedback divider value for PLL2, spread spectrum enabling for PLL2, and Data Byte 2 Output Enable Control Bits: Q0:Q11, Q13:Q14, Q15:Q16/nQ15:nQ16 outputs are enabled, Q12/nQ12 is disabled PLL2 M Divider Value: 80 SSC: Off BYPASS: Output divider clock source is the PLL Q12 Frequency (ƒ): 200MHz Data Byte 0 Control Bit Q16_EN Q15_EN Q14_EN Q13_EN Q12_ EN Q11_EN Q10_EN Q9_EN Power-up Default Value 1111 011 1 Data Byte 1 I C REGISTER SUMMARY Control Bit Q8_EN Q7_EN Q6_EN Q5_EN Q4_EN Q3_EN Q2_EN Q1_EN Power-up Default Value 11111111 Control Bit Q0_EN M4 M3 M2 M1 M0 SSC BYPASS Power-up Default Value 10100000 output divider clock source selection. The I C control registers and default settings are shown below: TABLE 3A. OUTPUT STATES FUNCTION TABLE Outputs Output Levels Disable State Q0:Q11 LVCMOS Hi-Z Q12/nQ12 HCSL Hi-Z Q13:Q14 LVCMOS Hi-Z Q15/nQ15 HCSL Hi-Z Q16/nQ16 HCSL Hi-Z Data Byte 3 Control Bit ƒ (Q12) Revision Reserved Reserved Reserved Reserved Reserved Reserved Power-up Default Value 01XXXXXX FUNCTION TABLES

©2016 Integrated Device Technology, Inc Revision A April 29, 20165 TABLE 3B. PLL2 FEEDBACK DIVIDER FUNCTION TABLE (Q12/nQ12, ÷10 MODE) VCO Frequency (MHz) Q12/nQ12 Frequency (MHz) Feedback Divide M4 M3 M2 M1 M0 1800 90 72 0 0 0 0 0 1825 91.25 73 0 0 0 0 1 1850 92.5 74 0 0 0 1 0 1875 93.75 75 0 0 0 1 1 1900 95 76 0 0 1 0 0 1925 96.25 77 0 0 1 0 1 1950 97.5 78 0 0 1 1 0 1975 98.75 79 0 0 1 1 1 2000 100 80 (default) 0 1 0 0 0 2025 101.25 81 0 1 0 0 1 2050 102.5 82 0 1 0 1 0 2075 103.75 83 0 1 0 1 1 2100 105 84 0 1 1 0 0 2125 106.25 85 0 1 1 0 1 2150 107.5 86 0 1 1 1 0 2175 108.75 87 0 1 1 1 1 2200 110 88 1 0 0 0 0 Not Used Not Used Not Used 10001

• • • 11111 TABLE 3C. PLL2, SSC MODE FUNCTION TABLE Register Bit Clock SourceBypass 0 (default) PLL Reference Clock (XTAL) TABLE 3D. BYPASS CLOCK SELECTION TABLE Register Bit Part RevisionRevision

0 Revision B

1 Revision C

TABLE 3E. Q12 FREQUENCY SELECTION TABLE TABLE 3F. REVISION DESCRIPTION TABLE Register Bit Output FrequencyQ12 Frequency 0 (default) 200MHz 1 100MHz Register Bit SS ModeSSC Of (default) Down-Spread – 0.5%

©2016 Integrated Device Technology, Inc Revision A April 29, 20166 START (ST) – defi ned as high-to-low transition on SDA while holding SCL HIGH. DATA - Between START and STOP cycles, SDA is synchronous with SCL. Data may change only when SCL is LOW and must be stable when SCL is HIGH. ACKNOWLEDGE (AK) – SDA is driven LOW before the SCL rising edge and held LOW until the SCL falling edge. STOP (SP) – defi ned as low-to-high transition on SDA while holding SCL HIGH. Data Byte values latched into control registers here.↑ I C INTERFACE - PROTOCOL The 844S2416 is a slave-only device and uses the standard I C protocol as shown in the below diagrams. The maximum SCL A serial transfer to the 844S2416 always consists of an address cycle followed by 4 data bytes. Once the 4 data bytes are loaded and the master generates a stop condition, the values in the serial I C INTERFACE - A WRITE EXAMPLE frequency is greater than 10MHz which is more than suffi cient for standard I C clock speeds. control register are latched into the M divider and control bits, and the device will move to the new frequency and any changes to the state of the control bits will take effect. ST Slave Address: 7 Bits R/W AK

1 Bit Refer to I

C Addressing section for address choices based on ADDR pin setting 1 Bit 1 Bit Data Byte 2: 8 Bits AK Q0_EN M4 M3 M2 M1 M0 SSC BYPASS 1 Bit Data Byte 0: 8 Bits AK Q16_EN Q15_EN Q14_EN Q13_EN Q12_EN Q11_EN Q10_EN Q9_EN 1 Bit Data Byte 1: 8 Bits AK Q8_EN Q7_EN Q6_EN Q5_EN Q4_EN Q3_EN Q2_EN Q1_EN 1 Bit I C ADDRESSING ADDR = 0 Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1001100 R /W

ADDR = 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1001110 R /W

ADDR = 0 ADDR = 1 The 844S2416 can be set to decode one of two addresses to minimize the chance of address confl ict on the I C bus. The address that is decoded is controlled by the setting of the ADDR pin as shown below. Data Byte 3: 8 Bits AK SP ƒ (Q12) Revision Reserved Reserved Reserved Reserved Reserved Reserved 1 Bit 1 Bit

extended periods may affect product reliability. TABLE 5. CRYSTAL CHARACTERISTICS

TABLE 6. AC CHARACTERISTICS, V NOTE 1: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 2: Only valid within the VCO operating range. NOTE 3: Spread Spectrum clocking enabled. NOTE 4: Measurement taken from differential waveform. ±100mV differential range. See Parameter Measurement Information Section. NOTE 6: Measurement taken from single-ended waveform. NOTES continued on next page.

©2016 Integrated Device Technology, Inc Revision A April 29, 20169 NOTE 7: Defi ned as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 8: Defi ned as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 9: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section. NOTE 10: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 11: Defi ned as the total variation of all crossing voltage of Rising Qx and Falling nQx. This is the maximum allowed variance in the V CROSS for any particular system. See Parameter Measurement Information Section. NOTE 12: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section.

©2016 Integrated Device Technology, Inc Revision A April 29, 201610 PARAMETER MEASUREMENT INFORMATION PERIOD JITTER 3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS GND 1.65V±5% -1.65V±5% VDD, VDDO_LVCMOS VDDA1 1.65V±5% Measurement Point33Ω 50Ω 50Ω33Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF 475Ω 475Ω IREF 3.3V±5% V DD 3.3V±5% VDDA1 LVCMOS CYCLE-TO-CYCLE JITTER Q0:Q11, Q13, Q14 ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

HCSL OUTPUT LOAD AC TEST CIRCUIT HCSL GND 0V 0V SCOPE IREF 3.3V±5% VDD This load condition is used for I DD , I DDA1 , I DDA2 and tjit measurements. LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 1.65V±5% VDDA2 3.3V±5% VDDA2 VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram

©2016 Integrated Device Technology, Inc Revision A April 29, 201611 HCSL CYCLE-TO-CYCLE JITTER LVCMOS OUTPUT RISE/FALL TIME PARAMETER MEASUREMENT INFORMATION, CONTINUED Q12, Q15:Q16 tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| nQ12, nQ15:nQ16 DIFFERENTIAL HCSL MEASUREMENT POINTS FOR RISE/FALL EDGE RATE DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING 20% 80% 80% 20% tR tF Q0:Q11, Q13, Q14 HCSL DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD

©2016 Integrated Device Technology, Inc Revision A April 29, 201616 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 844S2416. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 844S2416 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and HCSL Output Power Dissipation

• Power (core) MAX = V DD_MAX * (I DD + I DDA1 + I DDA2 ) = 3.465V * (170 + 9mA + 22mA) = 696.5mW
• Power (HCSL) MAX = 44.5mW/Loaded Output Pair If all outputs are loaded, the total power is 3 * 44.5mW = 133.5mW LVCMOS Output Power Dissipation
• Output Impedance R OUT Power Dissipation due to Loading 50Ω to V DDO Output Current I OUT = V DDO_MAX / [2 * (50Ω + R OUT
• Power Dissipation on the R OUT per LVCMOS output Power (R OUT ) = R OUT * (I OUT = 21Ω * (24.4mA) = 12.5mW per output
• Total Power Dissipation on the R OUT Total Power (R OUT ) = 12.5mW * 14 = 175mW
• Dynamic Power Dissipation at 24MHz and 25MHz Power Dynamic = V DDO_LVCMOS_MAX * I DDO_LVCMOS = 3.465V * 16mA = 55.44mW Total Power Dissipation
• Total Power = Power (core) + Power (HCSL) + Total Power (R OUT ) + Total Power (R OUT ) + Total Power (Dynamic) = 696.5mW + 133.5mW + 175mW + 55.44mW = 1060.4mW

TABLE 7. THERMAL RESISTANCE θJA FOR 56-LEAD VFQFN, FORCED CONVECTION wire and bond pad temperature remains below 125°C. 1 meter per second and a multi-layer board, the appropriate value is 27.5°C/W per Table 7.

TABLE 8. θ

TABLE 9. PACKAGE DIMENSIONS package dimensions are in Table 8 below.

TABLE 10. ORDERING INFORMATION TABLE 11. PIN 1 ORIENTATION IN TAPE AND REEL PACKAGING

©2016 Integrated Device Technology, Inc Revision A April 29, 201622 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 1 General Description - deleted HiperClocks logo. First sentence, deleted HiperClocks reference.Power Considerations - updated J unction Temperature sentence. 12/2/13 A T10 T11 Ordering Information - Added W part number. Added Pin 1 orientation table. 7/6/15 Updated data sheet header and footer. 4/29/16

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