844S012AKILFT

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Technical content

Features

• Two differential LVDS outputs (Bank A), configurable for PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz) clock signals
• Eight LVCMOS/LVTTL outputs (Bank B/C), 18 typical output impedance
• Two REF_OUT LVCMOS/LVTTL clock outputs 23 typical output impedance
• Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or one LVCMOS/LVTTL single-ended reference clock input
• Supports the following output frequencies: LVDS Bank A: 100MHz, 125MHz, 200MHz and 250MHz LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz, 100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz
• VCO: 2GHz
• Spread spectrum clock: ±0.25% center-spread, and -0.6% down-spread
• PLL bypass and output enable
• RMS period jitter: 17ps (maximum), QB outputs
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in a lead-free (RoHS 6) compliant package
• Replacement part: 844S012BKI-01LF/T 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VDD REF_OUT0 REF_OUT1 GND GND REF_IN VDD VDD REF_SEL XTAL_IN XTAL_OUT BYPASS REF_OE nMR VDDOC QC GND QBC_OE VDDA VDDA VDD GND GND GND QA0 nQA0 QA1 nQA1 GND GND SSC1 SSC0 F_SELB2 F_SELB1 F_SELB0 F_SELC2 F_SELC1 F_SELC0 F_SELA1 F_SELA0 QA_OE VDD QB6 GND QB5 VDDOB QB4 GND QB3 VDDOB VDDOB QB2 GND QB1 QB0 VDDOB 484950515253545556 47 46 45 44 43 844S012 56-Lead VFQFN 8mm x 8mm x 0.925mm package body K Package Top View Pin Assignment

844S012 REVISION B 08/25/15 2 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Block Diagram PLL VCO 2GHz M = ÷80 ÷NA ÷NC OSC QA0 nQA0 QA1 nQA1 QB0 QC QB1 QB2 QB3 QB4 QB5 QB6 REF_OUT0 REF_OUT1 QA_OE F_SELA[1:0] BYPASS REF_IN REF_OE REF_SEL nMR SSC[1:0] XTAL_IN XTAL_OUT 25MHz Pulldown Pullup 3F_SELC[2:0] Pulldown Pullup QBC_OE Pullup F_SELB[2:0] Pulldown Pulldown Pulldown Pulldown Pulldown Pullup Spread Spectrum ÷NB

844S012 REVISION B 08/25/15 3 ©2015 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1, 7, 14, 28, 29 V DD Power Core supply pins. impedance. LVCMOS/LVTTL interface levels. GND Power Power supply ground. selects crystal. See Table 3E. LVCMOS/LVTTL interface levels. 11 BYPASS Input Pulldown PLL bypass. When HIGH, bypasses PLL. When LOW, selects PLL. See Table 3J. LVCMOS/LVTTL interface levels. 12 REF_OE Input Pulldown Active HIGH REF_OUT enable/disable pin. See Table 3F. LVCMOS/LVTTL interface levels. device requires a reset signal after powerup. See Table 3G. LVCMOS/LVTTL interface levels. 16, 17 SSC1, SSC0 Input Pullup SSC control pins. See Table 3D. LVCMOS/LVTTL interface levels. F_SELB1, F_SELB0 Input Pulldown Frequency select pins for QBx outputs. See Table 3B. LVCMOS/LVTTL interface levels. F_SELC1, F_SELC0 Input Pulldown Frequency select pins for QC output. See Table 3C. LVCMOS/LVTTL interface levels. 24, 25 F_SELA1, F_SELA0 Input Pulldown Frequency select pins for QAx/nQAx outputs. See Table 3A. LVCMOS/LVTTL interface levels. 26 QA_OE Input Pullup Output enable pin for Bank A outputs. See Table 3H. LVCMOS/LVTTL interface levels. nQA0, QA0 Output Differential Bank A clock outp ut pairs. LVDS interface levels. DDA Power Analog supply pins. 39 QBC_OE Input Pullup Output enable pin for Bank B and Bank C outputs. See Table 3I. LVCMOS/LVTTL Interface levels. levels. 18 typical output impedance. 42 V DDOC Power Output supply pin for QC LVCMOS output. 43, 48, 52, 56 V DDOB Power Output supply pins for QBx LVCMOS outputs. levels. 18 typical output impedance.

844S012 REVISION B 08/25/15 4 ©2015 Integrated Device Technology, Inc. Table 2. Pin Characteristics

844S012 REVISION B 08/25/15 5 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Table 3C. F_SELC[2:0] Frequency Select Function Table Table 3D. SSC_SEL[1:0] Function Table Table 3E. REF_SEL Function Table Table 3F. REF_OE Function Table Inputs Output Frequenc y (25MHz Reference) F_SELC2 F_SELC1 F_SELC0 M Divider Value NC Divider Value QC – (MHz) 0 0 0 80 60 33.33 (default) 0 0 1 80 40 50 0 1 0 80 30 66.67 0 1 1 80 20 100 1 0 0 80 16 125 1 0 1 80 15 133.33 1 1 0 80 12 166.67 1 1 1 80 10 200 Inputs ModeSSC1 SSC0 0 0 0 to -0.6% Down-spread 0 1 ±0.25% Center-spread 1 0 ±0.25% Center-spread 1 1 SSC Off (default) Input REF_SEL Input Reference 0 (default) XTAL 1R E F _ I N Input REF_OE Function 0 (default) REF_OUT[0:1] - Disabled (High-Impedance)

1 REF_OUT[0:1] - Enabled

844S012 REVISION B 08/25/15 6 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Table 3G. nMR Function Table NOTE: This device requires a reset signal after power-up to function properly. Table 3H. QA_OE Function Table Table 3I. QBC_OE Function Table Table 3J. BYPASS Function Table Input nMR Function

0 Device reset, output divider - Disabled

1 (default) Output - Enabled Input QA_OE Function

0 QA[0:1], nQA[0:1] - Di sabled (High-Impedance)

1 (default) QA[0:1], nQA[0:1] - Enabled Input QBC_OE Function

0 QB[0:6] and QC - Disabled (High-Impedance)

1 (default) QB[0:6] and QC - Enabled Input BYPASS Function 0 (default) PLL

1 Bypass (reference ÷N)

844S012 REVISION B 08/25/15 7 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDOB = VDDOC = 3.3V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDDOx + 0.5V Outputs, VO (LVCMOS) -0.5V to V DDOx + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance,  JA 31.4°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.20 3.3 V DD V VDDOB, VDDOC Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 285 mA IDDA Analog Supply Current 20 mA IDDOA + IDDOB Output Supply Current 1m A

844S012 REVISION B 08/25/15 8 ©2015 Integrated Device Technology, Inc. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

844S012 REVISION B 08/25/15 9 ©2015 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = VDDOB = VDDOC = TA = -40°C to +85°C equilibrium has been reached under these conditions. NOTE 1: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOB/2.

844S012 REVISION B 08/25/15 10 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit LVDS Bank Skew LVCMOS Cycle-to-Cycle Jitter 3.3V LVCMOS Output Load AC Test Circuit LVCMOS Bank Skew LVDS Cycle-to-Cycle Jitter 3.3V ±5% VDDA VDD t sk(b) QAy QAx nQAy nQAx ➤➤ ➤➤ VDDOX VDDOX VDDOX tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QB[0:6], QC, REF_OUT0, REF_OUT1 SCOPE Qx GND VDDA 1.65V±5% -1.65V±5% VDD, VDDOB, VDDOC 1.65V±5% t sk(b) VDDOX VDDOX 2QBy QBx tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| QA[0:1] nQA[0:1]

844S012 REVISION B 08/25/15 11 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Parameter Measurement Information, continued LVCMOS Output Skew LVCMOS Rise/Fall Time LVCMOS Output Duty Cycle/Pulse Width/Period RMS Period Jitter LVDS Output Rise/Fall Time LVDS Output Duty Cycle/Pulse Width/Period t sk(o) VDDOX VDDOX 2Qy Qx 20% 80% 80% 20% tR tF QB[0:6], QC, REF_OUT0, REF_OUT1 QB[0:6], QC, REF_OUT0, REF_OUT1 VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram 20% 80% 80% 20% tR tF VOD QA[0:1] nQA[0:1] QA[0:1] nQA[0:1]

844S012 REVISION B 08/25/15 12 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Parameter Measurement Information, continued Offset Voltage Setup Differential Output Voltage Setup Applications Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_IN Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_IN to ground. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVDS Outputs All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

844S012 REVISION B 08/25/15 15 ©2015 Integrated Device Technology, Inc. at the receiver and a 100 differential transmission line environment. Figure 4. Typical LVDS Driver Termination

844S012 REVISION B 08/25/15 17 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Spread Spectrum Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32kHz triangle waveform is used with 0.6% down-spread (+0.0% / -0.6%) from the nominal output frequency. An example of a triangle frequency modulation profile is shown in Figure 7A below. The ramp profile can be expressed as: € Fnom = Nominal Clock Frequency in Spread Off mode € Fm = Nominal Modulation Frequency (30kHz) €  = Modulation Factor (0.6% down spread) The 844S012 triangle modulation frequency deviation will not exceed 0.7% down-spread from the nominal clock frequency (+0.0% / -0.6%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 7B. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.7%. The resulting spectral reduction will be greater than 5dB, as shown in Figure 7B. It is important to note the 844S012 5dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. Figure 7A. Triangle Frequency Modulation Figure 7B. 200MHz Clock Output In Frequency Domain (A) Spread-Spectrum OFF (B) Spread-Spectrum ON ➤1/fm0.5/fm Fnom (1 - δ) Fnom Frequency Time B A ' – 10 dBm G = 0.6% ➔➔

844S012 REVISION B 08/25/15 18 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the 844S012. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 844S012 is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum current at 85° is as follows: IDD_MAX = 270mA IDDA_MAX = 20mA IDDO_MAX = 1mA Core and LVDS Output Power Dissipation

• Power (core, LVDS) = V DD_MAX * (IDD + IDDA + IDDO) = 3.465V * (270mA + 20mA + 1mA) = 1008.315mW LVCMOS Output Power Dissipation
• Dynamic Power Dissipation at 200MHz, (QB, QC) Power (200MHz) = CPD * Frequency * (VDDO)2 = 4pF * 200MHz * (3.465V)2 = 9.6mW per output Total Power (200MHz) = 9.6mW * 8 = 76.7mW
• Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V)2 = 1.2mW per output Total Power (25MHz) = 1.2mW * 2 = 2.4mW Total Power Dissipation
• Total Power = Power (core, LVDS) + Total Power (200MHz) + Total Power (25MHz) = 1008.315mW + 76.7mW + 2.4mW = 1087.415mW

844S012 REVISION B 08/25/15 19 ©2015 Integrated Device Technology, Inc. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 31.4°C/W per Table 7 below. Table 7. Thermal Resistance JA for 56 Lead VFQFN, Forced Convection

844S012 REVISION B 08/25/15 20 ©2015 Integrated Device Technology, Inc. Table 8. JA vs. Air Flow Table for a 56 Lead VFQFN

844S012 REVISION B 08/25/15 21 ©2015 Integrated Device Technology, Inc. Table 9. Package Dimensions package dimensions are in Table 9.

1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)

844S012 REVISION B 08/25/15 22 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

844S012 REVISION B 08/25/15 23 ©2015 Integrated Device Technology, Inc. 844S012 Data Sheet CRYSTAL-TO-LV DS/LVCMOS FREQUENCY SYNTHESIZER Revision History Sheet Rev Table Page Description of Change Date B 1 PDN #CQ-15-04 Product Discontinuance Notice – Last Time buy Expires on August 14, 2016. 08/25/15

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This produ ct is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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