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Technical content
Features
- 4TH generation FemtoClock® NG technology
- Selectable 156.25MHz, 125MHz, 100MHz, 50MHz and 25MHz output clock signals synthesized from a 25MHz reference frequency
- Six differential LVDS clock outputs
- Crystal interface designed for a 25MHz crystal
- RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1MHz - 20MHz): 0.27ps (typical)
- Internal regulator for optimum noise rejection
- LVCMOS interface levels for the frequency select and output enable inputs
- Full 2.5V supply voltage
- Lead-free (RoHS 6) 48-lead VFQFN package
- -40°C to 85°C ambient operating temperature Block Diagram QA nQA QB0 nQB0 QB1 nQB1 QC nQC QD Pulldown Pulldown Pulldown Pullup Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pulldown OSC XTAL_IN XTAL_OUT REF_CLK REF_SEL MSEL FSELB FSELC FSELD ÷16 ÷20,÷25 ÷20,÷25 ÷50,÷100 ÷50÷100 PFD FemtoClock® NG VCO Pulldown 25MHz 25MHz 844N255I Data Sheet FemtoClock® NG Crystal-to-LVDS Clock Synthesizer
2©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet Pin Assignment GND REF_CLK REF_SEL XTAL_OUT XTAL_IN VDD MSEL VDD VDD GND GND GND 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 844N255I 48-lead VFQFN 7.0mm x 7.0mm x 0.925mm, package body K Package, Top View
36 GND
13 14 15 16 17 18 19 20 21 22 23 24 GNDB FSELB GNDC QC nQC VDDOC nOEC FSELC VDD FSELD nOED GNDD
Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to an internal input resistors. See Table 2, Pin Characteristics, for typical values. 1, 36, 37, 38, 39, 48 GND Power Power supply ground. 2V DDOA Power Output supply pin for the output QA. 3, 4 QA, nQA Output Differential clock output A. LVDS interface levels. 5 GNDA Power Power supply ground for the output QA. 6 nOEA Input Pulldown Output enable input. See Table 3G. LVCMOS/LVTTL interface levels. 7 nOEB Input Pulldown Output enable input. See Table 3H. LVCMOS/LVTTL interface levels. 8V DDOB Power Output supply pin for the Bank QB outputs. QB1, nQB1 Output Differential clock outputs (Bank B). LVDS interface levels. 13 GNDB Power Power supply ground for the outputs QB0 and QB1. 14 FSELB Input Pulldown Frequency select input for Bank B outputs. See Table 3C. LVCMOS/LVTTL interface levels. 15 GNDC Power Power supply ground for the output QC. 16, 17 QC, nQC Output Differential clock output C. LVDS interface levels. 18 V DDOC Power Output supply pin for the output QC. 19 nOEC Input Pulldown Output enable input. See Table 3I. LVCMOS/LVTTL interface levels. 20 FSELC Input Pullup Frequency select input for output QC. See Table 3D. LVCMOS/LVTTL interface levels. 21, 34, 40, 41, 43 V DD Power Core supply pin. 22 FSELD Input Pulldown Frequency select input for output QD. See Table 3E. LVCMOS/LVTTL interface levels. 23 nOED Input Pulldown Output enable input. See Table 3J. LVCMOS/LVTTL interface levels. 24 GNDD Power Power supply ground for the output QD. 25, 26 nQD, QD Output Differential clock output D. LVDS interface levels. 27 V DDOD Power Output supply pin for the output QD. 28 FSELE Input Pullup Frequency select input for output QE. See Table 3F. LVCMOS/LVTTL interface levels. 29 GNDE Power Power supply ground for the output QE. 30, 31 nQE, QE Output Differential clock output E. LVDS interface levels. 32 V DDOE Power Output supply pin for the output QE. 33 nOEE Input Pulldown Output enable input. See Table 3K. LVCMOS/LVTTL interface levels. 35 V DDA Power Analog power supply. 42 MSEL Input Pulldown Unused control input. Connect to logic LOW level. See Table 3A. LVCMOS/LVTTL interface levels. 46 REF_SEL Input Pulldown Reference select input. See Table 3B for function. LVCMOS/LVTTL interface levels. 47 REF_CLK Input Pulldown Alternative reference clock input. See Table 3B. LVCMOS/LVTTL interface levels.
Table 2. Pin Characteristics 0 (default) The crystal interface is selected as reference clock. Crystal frequency is 25MHz. 1 The external reference input REF_CLK is selected. NOTE: REF_SEL is an asynchronous control. NOTE: FSELB is an asynchronous control. NOTE: FSELC is an asynchronous control. NOTE: FSELD is an asynchronous control.
5©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet Table 3F. Output QE Frequency Select Function Table Input QE, nQE Frequency (MHz) FSELE 05 0 1 (default) 25 NOTE 1: FSELE is an asynchronous control. Table 3G. nOEA Output Enable Function Table Input QA, nQA Frequency (MHz) nOEA 0 (default) Output enabled
1 Output disabled in high-impedance state
NOTE: nOEA is an asynchronous control. Table 3H. nOEB Output Enable Function Table Input Operation nOEB 0 (default) QB0, nQB0 - QB1, nQB1 outputs are enabled
1 QB0, nQB0 - QB1, nQB1 Outputs are disabled (high-impedance)
NOTE: nOEB is an asynchronous control. Table 3I. nOEC Output Enable Function Table Input Operation nOEC 0 (default) QC, nQC output is enabled
1 QC, nQC output is disabled (high-impedance)
NOTE: nOEC is an asynchronous control. Table 3J. nOED Output Enable Function Table Input Operation nOED 0 (default) QD, nQD output is enabled
1 QD, nQD output is disabled (high-impedance)
NOTE: nOED is an asynchronous control. Table 3K. nOEE Output Enable Function Table Input Operation nOEE 0 (default) QE, nQE output is enabled
1 QE, nQE is disabled (high-impedance)
NOTE 1: nOEE is an asynchronous control.
6©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. NOTE 1: According to JEDEC/JESD 22-A114/22-C101. Table 4A. Power Supply DC Characteristics, VDD = VDDOX = 2.5V±5%, TA = -40°C to 85°C NOTE: VDDOX denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOE. NOTE: IDDOX denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOE. Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDOX = 2.5V±5%, TA = -40°C to 85°C NOTE: VDDOX denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOE. Item Rating Supply Voltage, VDD 3.63V Inputs, VI Crystal Inputs Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 29°C/W (0 mps) Storage Temperature, TSTG -65C to 150C ESD - Human Body Model, NOTE 1 2000V ESD - Charged Device Model, NOTE 1 1500V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5V 2.625 V VDDA Analog Supply Voltage V DD – 0.24 2.5V V DD V VDDOX Output Supply Voltage 2.375 2.5V 2.625 V IDD Power Supply Current 140 mA IDDA Analog Supply Current 24 mA IDDOx Output Supply Current 111 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current nOE[A:E], REF_CLK, REF_SEL, FSELB, FSELD, MSEL VDD = VIN = 2.625V 150 µA FSELC, FSELE V DD = VIN = 2.625V 5 µA IIL Input Low Current nOE[A:E], REF_CLK, REF_SEL, FSELB, FSELD, MSEL V DD = 2.625V, VIN = 0V -5 µA FSELC, FSELE V DD = 2.625V, VIN = 0V -150 µA
NOTE: VDDOX denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOE. Table 5. Crystal Characteristics
Table 6. AC Characteristics, VDD = VDDOX = 2.5V±5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: Characterized with 25MHz crystal, unless otherwise noted. NOTE: VDDOX denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOE. NOTE 1: Please refer to the phase noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
9©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet Typical Phase Noise at 156.25MHz Noise Power dBc Offset Frequency (Hz)
10©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet Parameter Measurement Information LVDS Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period RMS Phase Jitter Bank Skew Output Rise/Fall Time SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +– Float GND LVDSVDDA VDD, VDDOX nQX QX tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
tsk(b) nQB0 QB0 nQB1 QB1 20% 80% 80% 20% tR tF VOD nQx Qx
11©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet Parameter Measurement Information, continued Lock Time Differential Output Voltage Setup Offset Voltage Setup out out LVDSDC Input ➤ VOS/Δ VOS VDDO
and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
crystal load capacitors are required for proper operation. supplies to isolate from coupling into the internal PLL. Figure 5. 844N255I Application Schematic filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. suggests adding bulk capacitances in the local area of all devices.
23 FS ELD22 VD D
21 F SELC20 nO EC
19 VD DOC18 nQ C17 QC16 GND C15 FSELB
14 GNDB13
This section provides information on power dissipation and junction temperature for the 844N255I. Equations and example calculations are also provided. The total power dissipation for the 844N255I is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. wire and bond pad temperature remains below 125°C. and a multi-layer board, the appropriate value is 29°C/W per Table 7 below. Table 7. Thermal Resistance JA for 48 Lead VFQFN, Forced Convection
Table 8. JA vs. Air Flow Table for a 48-lead VFQFN
Table 9. PackageDimensions for 48 Lead VFQFN
- Type A: Chamfer on the paddle (near pin 1)
- Type C: Mouse bite on the paddle (near pin 1)
20©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet
Ordering Information
Table 10. Ordering Information Table
21©2016 Integrated Device Technology, Inc April 28, 2016 844N255I Data Sheet
Revision History
Revision Date Description of Change April 28, 2016 ▪ Remove ICS from the part number where needed. ▪ Ordering Information - Removed quantity from tape and reel. Deleted LF note below table. ▪ Updated data sheet header and footer.
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