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Technical content

Features

  • Designed for use in SAS, SAS-2, and SATA systems
  • Center (±0.17%) Spread Spectrum Clocking (SSC)
  • Down (-0.23% or -0.5%) SSC
  • Better frequency stability than SAW oscillators
  • One differential 2.5V LVDS output
  • Crystal oscillator interface designed for 25MHz (CL = 12pF) frequency
  • External fundamental crystal frequency ensures high reliability and low aging
  • Selectable output frequencies: 75MHz, 100MHz, 150MHz, 300MHz
  • Output frequency is tunable with external capacitors
  • RMS phase jitter @ 100MHz, using a 25MHz crystal (12kHz – 20MHz): 1.1936ps (typical)
  • 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging Block Diagrams FemtoClock™ PLLOSC nPLL_SEL 25MHz XTAL XTAL_IN XTAL_OUT 00 = 75MHz 01 = 100MHz 10 = 150MHz (default) 11 = 300MHz Q nQ SSC_SEL(1:0) F_SEL(1:0) Clock Output Control Logic 16-Lead TSSOP FemtoClock™ PLL OSC25MHz XTAL XTAL_IN XTAL_OUT 00 = SSC Off 01 = 0.5% Down-spread 10 = 0.23% Down-spread 11 = 0.5% Center-spread Q nQ SSC_SEL(1:0) SSC Output Control Logic 8-Lead SOIC Pulldown Pullup:Pulldown Pulldown:Pulldown Pulldown:Pulldown Pin Assignment nc SSC_SEL0 XTAL_IN XTAL_OUT GND F_SEL1 nPLL_SEL nQ Q V DD F_SEL0 VDDSSC_SEL1 GND nc nc 844441 16-Lead TSSOP, 4.4mm x 5.0mm Package 5 V DD XTAL_OUT XTAL_IN SSC_SEL0 GND Q nQ SSC_SEL1 844441 8-Lead SOIC, 3.90mm x 4.90mm Package 844441 Datasheet FemtoClock® SAS/ SATA Clock Generator

844441 Datasheet

Table 1. Pin Descriptions NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. nPLL_SEL Input Pulldown PLL Bypass pin. LVCMOS/LVTTL interface levels. Q, nQ Output Differential clock outputs. LVDS interface levels. GND Power Power supply ground.

3©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics,VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 4C. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA

16 Lead TSSOP

8 Lead SOIC

81.2°C/W (0 mps) 96.0°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 73 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 1.7 V DD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current F_SEL1 V DD = VIN = 2.5V 5 µA SSC_SEL[0:1], F_SEL0, nPLL_SEL VDD = VIN = 2.5V 150 µA IIL Input Low Current F_SEL1 V DD = 2.5V, VIN = 0V -150 µA SSC_SEL[0:1], F_SEL0, nPLL_SEL VDD = 2.5V, VIN = 0V -5 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 200 454 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1 1.375 V VOS VOS Magnitude Change 50 mV

Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz, 12pF quartz crystal. NOTE 1: Please refer to the Phase Noise plot.

5©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 Typical Phase Noise at 100MHz Noise Power (dBc / Hz) Offset Frequency (Hz)

6©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 Parameter Measurement Information 2.5V LVDS Output Load Test Circuit Output Rise/Fall Time Offset Voltage Setup RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup VDD 20% 80% 80% 20% tR tF VOD nQ Q nQ Q

7©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016

Application Information

Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface VCC XTAL_OUT XTAL_IN 100 100 Zo = 50 ohmsRsRo Zo = Ro + Rs .1uf LVCMOS Driver XTAL_OU T XTAL_I N Zo = 50 ohms C2 .1uf LVPECL Driver Zo = 50 ohms 50R3

8©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (Z T) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 2A can be used with either type of output structure. Figure 2B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. LVDS Termination LVDS Driver LVDS Driver LVDS Receiver LVDS ReceiverZT C ZO  ZT ZO  ZT ZT ZT Figure 2A. Standard Termination Figure 2B. Optional Termination

9©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 Figures 3A and 3B are example 844441 application schematics for either the 8 pin M package or the 16 pin G package. The schematic examples focus on functional connections and are not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In this example, the device is operated at V DD = 2.5V. A 12pF parallel resonant 25MHz crystal is used with tuning capacitors C1 = C2 =14pF, which are recommended for frequency accuracy. Depending on the variation of the parasitic stray capacity of the printed circuit board traces between the crystal and the Xtal_In and Xtal_Out pins, the values of C1 and C2 might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used, but this will require adjusting C1 and C2. In circuit board design, return the capacitors to ground through a single point contact close to the package. Two examples of terminations for LVDS receivers without built-in termination are shown in this schematic. In order to achieve the best possible filtering, it is recommended that the placement of the power filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. Figure 3A. 844441 Schematic Example XTA L_OU T XTA L_I N SS C _SE L0 SS C _SE L1 GN D nQ Q VDD 0.1uF Zo = 50 O hm 100 Zo = 50 O hm VD D Zo = 5 0 Oh m 0.1u F Zo = 5 0 Oh m 2.5V 10uF FB 1 BLM 18B B221SN 1 1 2 nQ Place the 0.1uF bypass cap directly adjacent to the VDD pin. Set Logic Input to '0' To L ogic In put pins Set Logic Input t o '1' Logic Input Pin Ex amples T o Lo gic In pu t pi ns SS C _SE L0 Q SS C _SE L1 Alt ernat e LVDS Terminat ion RU2 Not Instal l RU 1 RD 1 Not Instal l RD2 VDD VDD 14pF 14pF ,'7&U\\VWDO 1 3 25MHz(12pf) R20 0 XT AL_ IN XTA L_OU T 0.1u F nQ Q FOX 603-25-173 crystal

10©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 Figure 3B. 844441 Schematic Example 0.1 uF 14 pF 14 p F 10 0 Zo = 50 Ohm Zo = 50 Ohm Zo = 50 O hm Zo = 50 O hm C10 0.1 uF 2.5 V C1 1 10 uF nQ FB2 BLM18BB221SN1 Place one of the 0.1uF bypass caps directly adjacent to one of the VDD pins. Set Logic Input to ' 0' Set Logic Inpu t to ' 1' To Logic In p u t pins Logic Input Pin Examples To Logic In p u t pins SSC_SEL0 SSC_SEL1 Alternate LVDS Termination RU 3 RU 4 Not Install RD 3 RD 4 Not In stall VDD VD D C12 0. 1 uF nQ Q Q XTA L_OUT XTA L_IN SSC_SEL0 SSC_SEL1 F_SEL0 nPL L_SEL F_SEL1 nc nc nc Q nQ VDD VDD GN D GND VDD C13 0.1u F F_SEL1 F_SEL0 nPL L_SEL ,'7&U\\VWDO 1 3 25MHz(12pf) XT A L_ OU T XTA L _I N R1 9 0 FOX 603-25-173 crystal

11©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 This section provides information on power dissipation and junction temperature for the 844441. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 844441 is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Total Power MAX = VDD_MAX * IDD_MAX = 2.625V * 73mA = 191.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96°C/W per Table 6B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.192W * 96°C/W = 103.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W JA vs. Air Flow Linear Feet per Second 02 0 0 5 0 0 Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W

12©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 Table 7A. JA vs. Air Flow Table for a 16 Lead TSSOP Table 7B. JA vs. Air Flow Table for a 8 Lead SOIC Transistor Count The transistor count for 844441 is: 3374 JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W JA vs. Air Flow Linear Feet per Second 02 0 0 5 0 0 Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W

13©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 8A. Package Dimensions for 16 Lead TSSOP Reference Document: JEDEC Publication 95, MO-153 Package Outline - M Suffix for 8 Lead SOIC Table 8B. Package Dimensions for 8 Lead SOIC Reference Document: JEDEC Publication 95, MS-012 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 ccc C 0.08 C aaa C S NX b2 bbb C A B A NX L2 6.25 All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27  0° 8°

14©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016

Ordering Information

Table 9. Ordering Information Features Section, Crystal Oscillator bullet, added additional crystal recommendation. Crystal Characteristics Table - added crystal recommendation note. AC Characteristics Table - added additional crystal recommendation to 2nd note. Application Schematics - in schematics, added additional crystal recommendation. Deleted part number prefix/suffix throughout the datasheet. Updated datasheet header/footer. The 844441 datasheet is obsolete per PDN #CQ-15-04.

15©2016 Integrated Device Technology, Inc Revison E, November 2, 2016 DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole disc retion. Performance spec- ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided wit hout representation or warranty of any kind, wh ether express or implied, including, but not lim ited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantabilit y, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any lic ense under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an expres s, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other count ries. Other trademarks us ed herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

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