8442AKI-90LF | DigiCamel IC Datasheet

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ICS8442I-90 RENESAS | Alldatasheet

Document overview

Manufacturer or author: rdvorak
PDF pages: 20

Technical content

Features

Dual differential LVDS outputs FOUT1/nFOUT1 lags FOUT0/nFOUT0 by 90°
Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK
Output frequency range: 31.25MHz – 700MHz
Crystal input frequency range: 10MHz to 25MHz
VCO range: 250MHz – 700MHz
Parallel or serial interface for programming counter and output dividers
RMS period jitter: 7ps (maximum), (N= ÷1, ÷2, ÷4)
Cycle-to-cycle jitter: 34ps (maximum), (N= ÷1, ÷2)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For Replacement device use: 8442BYILF or 8T49N222 OSC VCO_SEL XTAL_SEL REF_CLK XT AL_IN XTAL_OUT S_LOAD S_DATA S_CLOCK nP_LOAD M[8:0] N[1:0] VCO PLL FOUT0 nFOUT0 FOUT1 nFOUT1 TEST CONFIGURATION INTERFACE LOGIC ÷ M PHASE DETECTOR ÷ 1 ÷ 2 ÷ 4 ÷ 8 MR 190˚Ø Pullup Pullup Pulldown Pulldown Pulldown Pulldown M5=Pullup; M[0:4], M[6:8]=Pulldown Pulldown Pulldown Pulldown 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nc GND XTAL_OUT REF_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR TEST VDD FOUT1 nFOUT1 VDD FOUT0 nFOUT0 GND VCO_SEL nP_LOAD XTAL_IN Pin AssignmentBlock Diagram ICS8442I-90

32 Lead VFQFN

5mm x 5mm x 0.925mm package body K Package Top View

ICS8442AKI-90 REVISION B JANUARY 31, 2014 2 ©2014 Integrated Device Technology, Inc. Characteristics, Table 5, NOTE 1. the M divider is also applied to the phase detector. LVDS output buffers. The divider provides a 50% output duty cycle. specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. the M divider and N output divider on each rising edge of S_CLOCK. Figure 1. Parallel & Serial Load Operations

00 L O W

11 C M O S f

NOTE: The NULL timing slot must be observed.

ICS8442AKI-90 REVISION B JANUARY 31, 2014 3 ©2014 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE 1: In bypass mode, VCO_SEL = 0, the differential outputs are phase aligned. Table 2. Pin Characteristics M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. 5, 6 N0, N1 Input Pulldown Determines output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. 8, 16 GND Power Power supply ground. parallel mode. LVCMOS / LVTTL interface levels. 10, 13 V DD Power Core supply pins. nFOUT1 Output Differential clock outputs for the synthesizer. Lags FOUT0, nFOUT0 by 90°. nFOUT0 Output Differential clock outputs for the synthesizer. LVDS interface levels.

17 MR Input Pulldown

the true outputs FOUTx to go low and the inverted outputs nFOUTx to go high. does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. edge of S_CLOCK. LVCMOS / LVTTL interface levels. 19 S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. 20 S_LOAD Input Pulldown Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. 21 V DDA Power Analog supply pin.

22 XTAL_SEL Input Pullup

Selects between crystal oscillator or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW. LVCMOS / LVTTL interface levels. 23 REF_CLK Input Pulldown Single-ended reference cloc k input. LVCMOS / LVTTL interface levels. XTAL_IN Input Crystal oscillator interf ace. XTAL_IN is the input, XTAL_OUT is the output. M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels.

27 VCO_SEL Input Pullup

VCO_SEL = 0, the differential outputs are phase aligned. NOTE 1. LVCMOS / LVTTL interface levels.

ICS8442AKI-90 REVISION B JANUARY 31, 2014 4 ©2014 Integrated Device Technology, Inc. ICS8442I-90 Data Sheet 700MHZ, CRYST AL-TO-LVDS FREQUENCY SYNTHESIZER Function Tables Table 3A. Parallel and Serial Mode Function Table NOTE: L = LOW H = HIGH X = Don’t care  = Rising edge transition  = Falling edge transition Table 3B. Programmable VCO Frequency Function Table (NOTE 1) NOTE 1: These M divide values and the resulting frequencies correspond to crystal or REF_CLK input frequency of 25MHz. Table 3C. Programmable Output Divider Function Table Inputs ConditionsMR nP_LOAD M N S_LOAD S_CLOCK S_DATA HXX X X X X Reset. When HIGH, forces the outputs to a differential LOW state (FOUTx = LOW and nFOUTx = HIGH), but does not effect loaded M, N, and T values. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L  Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LHX X L  Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LHX X  LD a t a Contents of the shift register are passed to the M divider and N output divider. LHX X  L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LHX X H  Data S_DATA passed directly to M divider as it is clocked. VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 1 0 000001010 2 7 5 1 1 000001011 6 5 0 2 6 000011010 6 7 5 2 7 000011011 7 0 0 2 8 000011100 Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 1 (default) 250 700 012 1 2 5 3 5 0 104 6 2 . 5 1 7 5 1 1 8 31.25 87.5

ICS8442AKI-90 REVISION B JANUARY 31, 2014 5 ©2014 Integrated Device Technology, Inc. ICS8442I-90 Data Sheet 700MHZ, CRYST AL-TO-LVDS FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDA = 3.3V±5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = 3.3V±5%, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Item Rating Supply Voltage, VCC 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 37C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.16 3.3 V DD V IDD Power Supply Current 210 mA IDDA Analog Supply Current 16 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current S_LOAD, REF_CLK, S_CLOCK, S_DATA, nP_LOAD V DD = VIN = 3.465V 150 µA M5, XTAL_SEL, VCO_SEL V DD = VIN = 3.465V 5 µA IIL Input Low Current S_LOAD, REF_CLK, S_CLOCK, S_DATA, nP_LOAD VDD = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL V DD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage TEST; NOTE 1 2.6 V VOL Output Low Voltage TEST; NOTE 1 0.5 V

ICS8442AKI-90 REVISION B JANUARY 31, 2014 7 ©2014 Integrated Device Technology, Inc. Table 7. AC Characteristics, VDD = VDDA = 3.3V±5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Not valid when VCO_SEL = 0.

ICS8442AKI-90 REVISION B JANUARY 31, 2014 8 ©2014 Integrated Device Technology, Inc. ICS8442I-90 Data Sheet 700MHZ, CRYST AL-TO-LVDS FREQUENCY SYNTHESIZER Parameter Measurement Information Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Rise/Fall Time Period Jitter Output Duty Cycle/Pulse Width/Period Setup and Hold Time 3.3V ±5% VCC VCCA tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

20% 80% 80% 20% tR tF VOD nFOUTx FOUTx VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nFOUTx FOUTx tHOLD tHOLD tSET -UP tSET -UP tSET -UP S_DATA SL_CLOCK S_LOAD M0:M8 N0:N1 nP_LOAD

ICS8442AKI-90 REVISION B JANUARY 31, 2014 9 ©2014 Integrated Device Technology, Inc. ICS8442I-90 Data Sheet 700MHZ, CRYST AL-TO-LVDS FREQUENCY SYNTHESIZER Parameter Measurement Information, continued Differential Output Voltage Setup Output Phase Relationship Offset Voltage Setup tphase(Ø) nFOUT0 FOUT0 nFOUT1 FOUT1

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8422I-90 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin. The 10 resistor can also be replaced by a ferrite bead. Figure 2. Power Supply Filtering resistor can be tied from the REF_CLK to ground.

ICS8442AKI-90 REVISION B JANUARY 31, 2014 14 ©2014 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8442I-90. Equations and example calculations are also provided. The total power dissipation for the ICS8442I-90 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 37°C/W per Table 8 below. Table 8. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection

Type A: Chamfer on the paddle (near pin 1)
Type C: Mouse bite on the paddle (near pin 1)

ICS8442AKI-90 REVISION B JANUARY 31, 2014 17 ©2014 Integrated Device Technology, Inc. ICS8442I-90 Data Sheet 700MHZ, CRYST AL-TO-LVDS FREQUENCY SYNTHESIZER Revision History Sheet Rev Table Page Description of Change Date B Product Discontinuation Notice - Last Time Buy Expires January 27, 2015, PDN# CQ-14-02 1/31/14

Ordering Information

Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS8442I-90 Data Sheet 700MHZ, CRYST AL-TO-LVDS FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved.

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Product Information

8442AKI-90LF specifications and overview.

Summary

700MHz, Crystal-to-LVDS Frequency Synthesizer 2019

Description

700MHz, Crystal-to-LVDS Frequency Synthesizer 2019

Source title 8442AKI-90LF Datasheet(PDF) - Renesas Technology Corp

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