84427

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Crystal-to-LVDS Integrated Frequency Synthesizer/Fanout Buffer 84427 DATASHEET 84427 REVISION B 5/6/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 84427 is a Crystal-to-LVDS Frequency Synthesizer/Fanout Buffer. The output frequency can be programmed using the frequency select pins. The low phase noise characteristics of the 84427 make it an ideal clock source for 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, OC3 and OC12 applications. BLOCK DIAGRAM PIN ASSIGNMENT

FEATURES

• Six LVDS outputs
• Crystal oscillator interface
• Output frequency range: 77.76MHz to 625MHz
• Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz
• RMS phase jitter at 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 3.4ps (typical) Phase noise: Offset Noise Power
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS-compliant package Q0:Q5 84427 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 V DD F_SEL0 F_SEL1 MR XTAL_IN XTAL_OUT F_SEL2 V DDA VDD PLL_SEL GND V DD PLL Feedback Divider OSC Output Divider XTAL_IN XTAL_OUT F_SEL2 PLL_SELMR F_SEL0 nQ0:nQ5 F_SEL1 FUNCTION TABLE Inputs Output Frequency F_XTAL MR F_SEL2 F_SEL1 F_SEL0 F_OUT X1 X X X L O W 19.44MHz 0 1 0 0 77.76MHz 19.44MHz 0 1 0 1 155.52MHz 19.44MHz 0 1 1 0 311.04MHz 19.44MHz 0 1 1 1 622.08MHz 25MHz 0 0 0 0 78.125MHz 25MHz 0 0 0 1 156.25MHz 25MHz 0 0 1 0 312.5 MHz 25MHz 0 0 1 1 625MHz 25.5MHz 0 0 0 1 159.375MHz

84427 DATA SHEET

2 REVISION B 5/6/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1, 2 Q0, nQ0 Output Differential output pair. LVDS interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVDS interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVDS interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVDS interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVDS interface levels. 11, 12 Q5, nQ5 Output Differential output pair. LVDS interface levels.

15 PLL_SEL Input Pullup

Selects between the PLL and crystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL_IN and XTAL_OUT. LVCMOS / LVTTL interface levels. DDA Power Analog supply pin. 18 F_SEL2 Input Pullup Feedback frequency select pin. LVCMOS/LVTTL interface levels.

21 MR Input Pulldown

enabled. LVCMOS / LVTTL interface levels. 22 F_SEL1 Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. 23 F_SEL0 Input Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

84427 D ATA SHEET

3 CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.72 3.3 V DD V IDD Power Supply Current 300 mA IDDA Analog Supply Current 30 mA TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 375 475 575 mV Δ VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.3 1.45 1.6 V Δ VOS VOS Magnitude Change 50 mV ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to VDD + 0.5V Outputs, I O Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θJA 50°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current MR, F_SEL1 VDD = VIN = 3.465V 150 µA PLL_SEL, F_SEL0, F_SEL2 VDD = VIN = 3.465V 5 µA IIL Input Low Current MR, F_SEL1 VDD = 3.465V, VIN = 0V -5 µA PLL_SEL, F_SEL0, F_SEL2 V DD = 3.465V, VIN = 0V -150 µA

4 REVISION B 5/6/15

TABLE 4. CRYSTAL CHARACTERISTICS TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C See Parameter Measurement Information section. NOTE 1: See Phase Noise Plots. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points.

5 CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER TYPICAL PHASE NOISE AT 155.52MHZ 155.52MHz RMS Phase Noise Jitter 12kHz to 20MHz = 3.4ps (typical) 156.25MHz RMS Phase Noise Jitter 12kHz to 20MHz = 3.1ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) PHASE NOISE (dBc)HZ OFFSET FREQUENCY (HZ) PHASE NOISE (dBc)HZ TYPICAL PHASE NOISE AT 156.25MHZ 10 100 1k 10k 100k 1M 10M 100M -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10Gb Ethernet Filter Raw Phase Noise Data Phase Noise Result by adding 10Gb Ethernet Filter to raw data SONET Filter Raw Phase Noise Data Phase Noise Result by adding a SONET Filter to raw data

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

6 REVISION B 5/6/15

PARAMETER MEASUREMENT INFORMATION OFFSET VOLTAGE SETUP OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER DIFFERENTIAL OUTPUT VOLTAGE SETUP 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEWCYCLE-TO-CYCLE JITTER

7 CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 84427 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING Figure 2. CRYSTAL INPUt INTERFACE and C2 values can be slightly adjusted for different board layouts.

8 REVISION B 5/6/15

recommend that there is no trace attached. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE and R2 in parallel should equal the transmission line impedance. also be accomplished by removing R1 and making R2 50Ω.

9 CRYSTAL-TO-LVDS

100 Ohm Differiential Transmission Line

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION are used, it is recommended to terminate the un-used outputs. F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

10 REVISION B 5/6/15

The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C3, C5 and C6, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.  The differential 100 Ω output traces should have the same length.  Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.  Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.  To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.  Make sure no other signal traces are routed between the clock trace pair.  The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 20 (XTAL_IN) and 19 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. FIGURE 5B. PCB BOARD LAYOUT FOR 84427 VDDA C1 C5 Signals ICS84427 VDD Pin1 VIAC16 C11

50 Ohm Traces

11 CRYSTAL-TO-LVDS

This section provides information on power dissipation and junction temperature for the 84427. Equations and example calculations are also provided. The total power dissipation for the 84427 is the sum of the core power plus the power dissipated in the load(s). DD = 3.3V + 5% = 3.465V, which gives worst case results. the device. The maximum recommended junction temperature for the devices is 125°C. moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below. and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

12 REVISION B 5/6/15

TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

13 CRYSTAL-TO-LVDS

TABLE 8. PACKAGE DIMENSIONS

14 REVISION B 5/6/15

TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS complaint.

15 CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page Description of Change Date BT 9 1 4 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column.Added Contact Page. 7/27/10 B T9 Product Discontinuation Notice - PDN CQ-15-03. Ordering Information - removed leaded devices. 5/6/15

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