844256DGLF | DigiCamel IC Datasheet

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ICS844256D IDT | Alldatasheet

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PDF pages: 18

Technical content

Features

Six differential LVDS output pairs
Crystal oscillator interface
Output frequency range: 62.5MHz - 625MHz
Crystal input frequency range:15.625MHz - 25.5MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.43ps (typical)
Full 3.3V or mixed 3.3V core, 2.5V output supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package Divider Function Table Inputs Function FB_SEL N_SEL1 N_SEL0 M Divider Value N Divider Value M/N Divider Value 000 2 5 1 2 5 0 0 1 25 2 12.5 010 2 5 4 6 . 2 5 0 1 1 25 (default) 5 5 100 3 2 1 3 2 101 3 2 2 1 6 110 3 2 4 8 111 3 2 8 4 VDDO Q3 VDDO VDDA nQ3 nQ2 Q4 Q2 nQ4 nQ1 Q5 Q1 nQ5 nQ0 N_SEL1 N_SEL0 VDD XTAL_OUT FB_SEL XTAL_IN Q0 GND PLL_BYPASS GND PLL M Feedback Divider OSC nQ3 nQ4 nQ5 nQ0 nQ1 nQ2 N_SEL0 N_SEL1 PLL_BYPASS FB_SEL XTAL_IN XTAL_OUT Pulldown Pullup Pullup Pullup N Output Divider ICS844256D 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.925mm package body G Package Top View Block Diagram Pin Assignment

ICS844256DG REVISION A AUGUST 5, 2010 2 ©2010 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 V DDO Power Output supply pins. 3, 4 nQ2, Q2 Output Differential out put pair. LVDS interface levels. 5, 6 nQ1, Q1 Output Differential out put pair. LVDS interface levels. 7, 8 nQ0, Q0 Output Differential out put pair. LVDS interface levels.

9 PLL_BYPASS Input Pullup

divider. LVCMOS / LVTTL interface levels. 10 V DDA Power Analog supply pin. 11 V DD Power Core supply pin. 12 FB_SEL Input Pulldown Feedback and output frequency select pin. LVCMOS/LVTTL interface levels. XTAL_OUT Input Crystal oscillator interf ace. XTAL_IN is the input. XTAL_OUT is the output. N_SEL1 Input Pullup Feedback and output frequency select pins. LVCMOS/LVTTL interface levels. 16, 17 GND Power Power supply ground. 19, 20 nQ5, Q5 Output Differential out put pair. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential out put pair. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential out put pair. LVDS interface levels.

ICS844256DG REVISION A AUGUST 5, 2010 4 ©2010 Integrated Device Technology, Inc. ICS844256D Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 32.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.11 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 172 mA IDDA Analog Supply Current 11 mA IDDO Output Supply Current 72 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.11 3.3 V DD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 172 mA IDDA Analog Supply Current 11 mA IDDO Output Supply Current 70 mA

ICS844256DG REVISION A AUGUST 5, 2010 6 ©2010 Integrated Device Technology, Inc. ICS844256D Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to the Phase Noise Plot. Table 6B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to the Phase Noise Plot. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 62.5 625 MHz tsk(o) Output Skew; NOTE 1, 2 65 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 125MHz (1.875MHz – 20MHz) 0.43 ps t R / tF Output Rise/Fall Time 20% to 80% 200 565 ps odc Output Duty Cycle ≤ 312.5MHz 47 53 % > 312.5MHz 45 55 % tLOCK PLL Lock Time 25 ms Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 62.5 625 MHz tsk(o) Output Skew; NOTE 1, 2 65 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 125MHz (1.875MHz – 20MHz) 0.43 ps t R / tF Output Rise/Fall Time 20% to 80% 200 550 ps odc Output Duty Cycle ≤ 312.5MHz 47 53 % > 312.5MHz 44 56 % tLOCK PLL Lock Time 25 ms

ICS844256DG REVISION A AUGUST 5, 2010 7 ©2010 Integrated Device Technology, Inc. ICS844256D Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Typical Phase Noise at 125MHz (3.3V core/3.3V output) Typical Phase Noise at 125MHz (3.3V core/2.5V output) 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.43ps (typical) Offset Frequency (Hz) Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.43ps (typical) Offset Frequency (Hz) Noise Power dBc Hz

ICS844256DG REVISION A AUGUST 5, 2010 8 ©2010 Integrated Device Technology, Inc. ICS844256D Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Parameter Measurement Information 3.3V Core/3.3V Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 3.3V Core/2.5V Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDD, VDDA VDDO tsk(o) Qx nQx Qy nQy nQ[0:5] Q[0:5] tPW tPERIOD tPW tPERIOD odc = x 100% Qx nQx Float GND ++ – POWER SUPPL Y SCOPE LVDS VDD VDDA VDDO Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power nQ[0:5] Q[0:5] 20% 80% 80% 20% tR tF VOD

ICS844256DG REVISION A AUGUST 5, 2010 9 ©2010 Integrated Device Technology, Inc. ICS844256D Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Parameter Measurement Information, continued Offset Voltage Setup Differential Output Voltage Setup

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844256D provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering

ICS844256DG REVISION A AUGUST 5, 2010 11 ©2010 Integrated Device Technology, Inc. resistance is not required but can be added for additional protection. at the receiver and a 100Ω differential transmission line environment. Figure 4. Typical LVDS Driver Termination

ICS844256DG REVISION A AUGUST 5, 2010 12 ©2010 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Enhance Leadframe Base Package, Amkor Technology. Figure 5. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

ICS844256DG REVISION A AUGUST 5, 2010 14 ©2010 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS844256D. Equations and example calculations are also provided. The total power dissipation for the ICS844256D is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. multi-layer board, the appropriate value is 32.1°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 24 Lead TSSOP, E-Pad, Forced Convection

ICS844256DG REVISION A AUGUST 5, 2010 16 ©2010 Integrated Device Technology, Inc. ICS844256D Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP, E-Pad Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 24 A 1.10 A1 0.05 0.15 A2 0.85 0.90 0.95 b 0.19 0.30 b1 0.19 0.22 0.25 c 0.09 0.20 c1 0.09 0.127 0.16 D 7.70 7.90 E 6.40 Basic E1 4.30 4.40 4.50 e 0.65 Basic L 0.50 0.60 0.70 P 5.0 5.5 P1 3.0 3.2 α 0° 8° ααα 0.076 bbb 0.10

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

ICS844256D Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.

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Product Information

844256DGLF specifications and overview.

Summary

FemtoClock짰Crystal-to-LVDS Frequency Synthesizer w/Integrated Fanout Buffer

Description

FemtoClock짰Crystal-to-LVDS Frequency Synthesizer w/Integrated Fanout Buffer

Source title 844256DGLF Datasheet(PDF) - Integrated Device Technology

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