ICS844251I-14 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 15
Technical content
Features
- One differential LVDS output pair
- Crystal oscillator interface designed for an 18pF, parallel resonant crystal (23.2MHz – 30MHz)
- Output frequency ranges: 145MHz – 187.5MHz and 580MHz – 750MHz
- VCO range: 580MHz – 750MHz
- RMS phase jitter at 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.53ps (typical)
- Full 2.5V output supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- For functional replacement part use 8T49N242 Common Configuration Table HiPerClockS™ ICS Inputs Output Frequency Range (MHz)Crystal Frequency (MHz) FREQ_SEL M N Multiplication Value M/N 25 1 25 1 25 625 26.67 1 25 1 25 666.67 25 (default) 0 25 4 6.25 156.25 VDDA GND XTAL_OUT XTAL_IN VDD Q nQ FREQ_SEL ICS844251I-14
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body G Package Top View OSC Phase Detector VCO 580MHz - 750MHz M = ÷25 (fixed) FREQ_SEL N 0 (default) ÷4 1 ÷1 Pulldown XTAL_IN XTAL_OUT FREQ_SEL Q nQ Block Diagram Pin Assignment PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
ICS844251BGI-14 REVISION A June 6, 2016 2 ©2016 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDA Output Analog supply pin. 2 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. 5 FREQ_SEL Input Pulldown Frequency select pi n. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential output pair. LVDS interface levels. 8V DD Power Core supply pin.
ICS844251BGI-14 REVISION A June 6, 2016 3 ©2016 Integrated Device Technology, Inc. ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 3C. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputts 0V to VDD -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 129.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.10 2.5 V DD V IDD Power Supply Current 95 mA IDDA Analog Supply Current 10 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 1.7 V DD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current V DD = VIN = 2.625V 150 µA IIL Input Low Current V DD = 2.625V, VIN = 0V -5 µA Symbol Parameter Test Conditions Minimum T ypical Maximum Units VOD Differential Output Voltage 247 454 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.0 1.4 V VOS VOS Magnitude Change 50 mV
ICS844251BGI-14 REVISION A June 6, 2016 4 ©2016 Integrated Device Technology, Inc. Table 4. Crystal Characteristics Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots.
ICS844251BGI-14 REVISION A June 6, 2016 5 ©2016 Integrated Device Technology, Inc. ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Typical Phase Noise at 156.25MHz Typical Phase Noise at 625MHz Ethernet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.54ps (typical) Offset Frequency (Hz) Noise Power dBc Hz Noise Power dBc Hz Ethernet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps (typical) Offset Frequency (Hz)
ICS844251BGI-14 REVISION A June 6, 2016 6 ©2016 Integrated Device Technology, Inc. ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information LVDS Output Load AC Test Circuit Output Rise/Fall Time D IFFERENTIAL OUTPUT VOLTAGE SETUP RMS Phase Jitter Output Duty Cycle/Pulse Width/Period O FFSET VOLTAGE SETUP SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND VDD VDDA 20% 80% 80% 20% tR tF VOD nQ Q Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ Q
ICS844251BGI-14 REVISION A June 6, 2016 9 ©2016 Integrated Device Technology, Inc. Figure 5 shows an example of ICS844251I-14 application schematic. capacitor should be located as close as possible to the power pin. 100 resistor as close to the receiver as possible. Figure 5. ICS844251I-14 Schematic Example
25 MHz
ICS844251BGI-14 REVISION A June 6, 2016 10 ©2016 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS844251I-14. Equations and example calculations are also provided. The total power dissipation for the ICS844251I-14 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 129.5.°C/W per Table 6 below. Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
ICS844251BGI-14 REVISION A June 6, 2016 11 ©2016 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP Table 8. Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP
ICS844251BGI-14 REVISION A June 6, 2016 12 ©2016 Integrated Device Technology, Inc. ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS844251BGI-14 REVISION A June 6, 2016 13 ©2016 Integrated Device Technology, Inc. ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Revision History Sheet Rev Table Page Description of Change Date A Front page corrected Genneraator typo to Generator. Absolute Maximum Ratings, updated Inputs. Updated Overdriving the XTAL Interface section. 2/24/10 A Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 6/3/16
ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2016. All rights reserved.
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