844251BG-15LF

ICS844251-15 RENESAS | Alldatasheet

Document overview

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• PDF pages: 16

Technical content

Features

• One differential LVDS output pair
• Crystal oscillator interface designed for 18pF , parallel resonant crystal (23.2MHz – 30MHz)
• Output frequency ranges: 116MHz – 150MHz and 580MHz – 750MHz
• VCO range: 580MHz – 750MHz
• RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.46ps (typical)
• Full 3.3V or 2.5V output supply modes
• 0°C to 70°C ambient operating temperature
• Available in a lead-free (RoHS 6) package Common Configuration Table HiPerClockS™ ICS Inputs Output Frequency Range (MHz)Crystal Frequency (MHz) FREQ_SEL M N Multiplication Value M/N 25 1 25 1 25 625 26.667 1 25 1 25 666.67 25 (default) 0 25 5 5 125 26.667 0 25 5 5 133.33 VDDA GND XTAL_OUT XTAL_IN VDD Q nQ FREQ_SEL ICS844251-15

8 Lead TSSOP

4.40mm x 3.0mm x 0.925mm package body G Package Top View OSC Phase Detector VCO 580MHz - 750MHz M = ÷25 (fixed) FREQ_SEL N 0 (default) ÷5 1 ÷1 Q nQ FREQ_SEL XTAL_IN XTAL_OUT Pulldown Block Diagram Pin Assignment

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 2 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDA Power Analog supply pin. 2 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential outp ut pair. LVDS interface levels. 8V DD Power Core supply pin.

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 3 ©2009 Integrated Device Technology, Inc. ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 3B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.10 3.3 V DD V IDD Power Supply Current 100 mA IDDA Analog Supply Current 10 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.10 2.5 V DD V IDD Power Supply Current 95 mA IDDA Analog Supply Current 10 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V IIH Input High Current V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current V DD = 3.465V or 2.625V, VIN = 0V -5 µA

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 4 ©2009 Integrated Device Technology, Inc. Table 4. Crystal Characteristics

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 5 ©2009 Integrated Device Technology, Inc. ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency FREQ_SEL = 0 116 150 MHz FREQ_SEL = 1 580 750 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 125MHz, Integration Range: 1.875MHz – 20MHz 0.46 ps 625MHz, Integration Range: 1.875MHz – 20MHz 0.35 ps tR / tF Output Rise/Fall Time 20% to 80% 70 550 ps odc Output Duty Cycle FREQ_SEL = 0 48 52 % FREQ_SEL = 1 46 54 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency FREQ_SEL = 0 116 150 MHz FREQ_SEL = 1 580 750 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 125MHz, Integration Range: 1.875MHz – 20MHz 0.46 ps 625MHz, Integration Range: 1.875MHz – 20MHz 0.35 ps t R / tF Output Rise/Fall Time 20% to 80% 70 550 ps odc Output Duty Cycle FREQ_SEL = 0 48 52 % FREQ_SEL = 1 46 54 %

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 6 ©2009 Integrated Device Technology, Inc. ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Typical Phase Noise at 125MHz (3.3V) Ethernet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.46ps (typical) Offset Frequency (Hz) Noise Power dBc Hz

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 7 ©2009 Integrated Device Technology, Inc. ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Typical Phase Noise at 625MHz (3.3V) Ethernet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.35ps (typical) Offset Frequency (Hz) Noise Power dBc Hz

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 8 ©2009 Integrated Device Technology, Inc. ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Rise/Fall Time RMS Phase Jitter 2.5V LVDS Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period Offset Voltage Setup SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDD VDDA 20% 80% 80% 20% tR tF VOD nQ Q Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND LVDS VDD VDDA nQ Q tPW tPERIOD tPW tPERIOD odc = x 100% out out LVDSDC Input ➤ VOS/∆ VOS VDD

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 9 ©2009 Integrated Device Technology, Inc. ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information, continued Differential Output Voltage Setup

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844251-15 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 11 ©2009 Integrated Device Technology, Inc. Figure 4. Typical LVDS Driver Termination

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 12 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS844251-15. Equations and example calculations are also provided. The total power dissipation for the ICS844251-15 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. 125°C ensures that the bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 129.5.°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 13 ©2009 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP

ICS844251BG-15 REVISION A SEPTEMBER 18, 2009 14 ©2009 Integrated Device Technology, Inc. ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS844251-15 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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