ICS844251-14 IDT | Alldatasheet

Document overview

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Technical content

Features

  • One differential LVDS output pair
  • Crystal oscillator interface designed for 18pF , parallel resonant crystal (23.2MHz – 30MHz)
  • Output frequency ranges: 145MHz – 187.5MHz and 580MHz – 750MHz
  • VCO range: 580MHz – 750MHz
  • RMS phase jitter at 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.53ps (typical)
  • Full 3.3V or 2.5V output supply modes
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Common Configuration Table HiPerClockS™ ICS Inputs Output Frequency Range (MHz)Crystal Frequency (MHz) FREQ_SEL M N Multiplication Value M/N 25 1 25 1 25 625 26.67 1 25 1 25 666.67 25 (default) 0 25 4 6.25 156.25 VDDA GND XTAL_OUT XTAL_IN VDD Q nQ FREQ_SEL ICS844251-14

8 Lead TSSOP

4.40mm x 3.0mm x 0.925mm package body G Package Top View OSC Phase Detector VCO 580MHz - 750MHz M = ÷25 (fixed) FREQ_SEL N 0 (default) ÷4 1 ÷1 Pulldown XTAL_IN XTAL_OUT FREQ_SEL Q nQ Block Diagram Pin Assignment

Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDA Output Analog supply pin. 2 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL _IN is the input, XTAL_OUT is the output. 5 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential output pair. LVDS interface levels. 8V DD Power Core supply pin.

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 3 ICS844251BG-14 REV. A MAY 1, 2009 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 3B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.10 3.3 V DD V IDD Power Supply Current 100 mA IDDA Analog Supply Current 10 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.10 2.5 V DD V IDD Power Supply Current 95 mA IDDA Analog Supply Current 10 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V IIH Input High Current V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current V DD = 3.465V or 2.625V, VIN = 0V -5 µA

Table 4. Crystal Characteristics

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 5 ICS844251BG-14 REV. A MAY 1, 2009 Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency FREQ_SEL = 0 145 187.5 MHz FREQ_SEL = 1 580 750 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 156.25MHz, Integration Range: 1.875MHz – 20MHz 0.53 ps 625MHz, Integration Range: 1.875MHz – 20MHz 0.45 ps tR / tF Output Rise/Fall Time 20% to 80% 70 550 ps odc Output Duty Cycle FREQ_SEL = 0 48 52 % FREQ_SEL = 1 46 54 % Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency FREQ_SEL = 0 145 187.5 MHz FREQ_SEL = 1 580 750 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 156.25MHz, Integration Range: 1.875MHz – 20MHz 0.54 ps 625MHz, Integration Range: 1.875MHz – 20MHz 0.45 ps t R / tF Output Rise/Fall Time 20% to 80% 70 550 ps odc Output Duty Cycle FREQ_SEL = 0 48 52 % FREQ_SEL = 1 46 54 %

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 6 ICS844251BG-14 REV. A MAY 1, 2009 Typical Phase Noise at 156.25MHz (3.3V) Typical Phase Noise at 625MHz (3.3V) Ethernet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical) Offset Frequency (Hz) Ethernet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps Offset Frequency (Hz) Noise Power dBc Hz Noise Power dBc Hz

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 7 ICS844251BG-14 REV. A MAY 1, 2009 Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Rise/Fall Time RMS Phase Jitter 2.5V LVDS Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period O FFSET VOLTAGE SETUP SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDD VDDA 20% 80% 80% 20% tR tF VOD nQ Q Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND LVDS VDD VDDA nQ Q tPW tPERIOD tPW tPERIOD odc = x 100% out out LVDSDC Input ➤ VOS/∆ VOS VDD

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 8 ICS844251BG-14 REV. A MAY 1, 2009 Parameter Measurement Information, continued DIFFERENTIAL OUTPUT VOLTAGE SETUP

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The ICS844251-14 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering

matched load termination of 100Ω across near the receiver input. Figure 4. Typical LVDS Driver Termination

schematic. In this example, the device is operated at VDD = 3.3V. Figure 5. ICS844251-14 Schematic Example

25 MHz

This section provides information on power dissipation and junction temperature for the ICS844251-14. Equations and example calculations are also provided. load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 129.5.°C/W per Table 6 below. of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection

Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP Table 8. Package Dimensions

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 14 ICS844251BG-14 REV. A MAY 1, 2009

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT product for use in life support devices or critical medical instruments.

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 15 ICS844251BG-14 REV. A MAY 1, 2009 Revision History Sheet Rev Table Page Description of Change Date A 11 Added schematic layout. 5/1/09

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR www.IDT.com © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contact IDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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