844244I-04 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: epieczon
  • PDF pages: 17

Technical content

Features

  • Four differential LVDS output pairs
  • Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz – 28.3MHz)
  • Output frequency range: 125MHz – 170MHz
  • VCO range: 500MHz – 680MHz
  • RMS phase jitter at 150MHz, using a 25MHz crystal (12kHz – 20MHz): 0.9ps (typical) @ 3.3V
  • Full 3.3V or 2.5V output supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package OSC Phase Detector VCO 500MHz - 680MHz ÷24 nQ0 nQ1 nQ2 XTAL_IN XTAL_OUT nQ3 nQ0 VDD nQ1 GND XTAL_IN XTAL_OUTVDD VDDA GND nQ3 VDD nQ2 Pin Assignment 844244I-04

16 Lead TSSOP

4.4mm x 5.0mm package body Block Diagram

Table 1. Pin Descriptions NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. 1, 2 Q2, nQ2 Output Differential clock output pair. LVDS interface levels. 3, 8, 14 V DD Power Core supply pins. 4, 5 Q3, nQ3 Output Differential clock output pair. LVDS interface levels. 6, 11 GND Power Power supply ground. 7V DDA Power Analog supply pin. 9, 10 XTAL_OUT, XTAL_IN Input Crystal oscillator interfac e. XTAL_IN is the input, XTAL_OUT is the output. 12, 13 nQ1, Q1 Output Differential clo ck output pair. LVDS interface levels. 15, 16 nQ0, Q0 Output Differential clo ck output pair. LVDS interface levels.

Table 3. Crystal Characteristics

FEMTOCLOCK® CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR 4 REVISION B 10/15/15 844244I-04 DATA SHEET Table 4A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz crystal, f OUT @ 150MHz. NOTE 1: Refer to Phase Noise Plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. Table 4B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz crystal, fOUT @ 150MHz. NOTE 1: Refer to Phase Noise Plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 125 150 170 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 150MHz, Integration Range: 12kHz – 20MHz 0.9 ps tsk(o) Output Skew; NOTE 2, 3 65 ps tR / tF Output Rise/Fall Time 20% to 80% 250 650 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 125 150 170 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 150MHz, Integration Range: 12kHz – 20MHz 1.1 ps tsk(o) Output Skew; NOTE 2, 3 65 ps tR / tF Output Rise/Fall Time 20% to 80% 200 650 ps odc Output Duty Cycle 48 52 %

REVISION B 10/15/15 5 FEMTOCLOCK ® CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR 844244I-04 DATA SHEET Typical Phase Noise at 150MHz (3.3V) 150MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.9ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

FEMTOCLOCK® CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR 6 REVISION B 10/15/15 844244I-04 DATA SHEET Typical Phase Noise at 150MHz (2.5V) 150MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.1ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

REVISION B 10/15/15 7 FEMTOCLOCK ® CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR 844244I-04 DATA SHEET Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 2.5V LVDS Output Load AC Test Circuit Output Rise/Fall Time RMS Phase Jitter 3.3V ±5% VDD VDDA nQx Qx nQy Qy nQ[0:3] Q[0:3] SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND VDD VDDA 20% 80% 80% 20% tR tF VOD nQ[0:3] Q[0:3]

FEMTOCLOCK® CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR 8 REVISION B 10/15/15 844244I-04 DATA SHEET Parameter Measurement Information, continued Offset Voltage Setup Differential Output Voltage Setup

capacitor should be located as close as possible to the power pin. 100 resistor as close to the receiver as possible. Figure 5. 844244I-04 Application Schematic

25 MHz

This section provides information on power dissipation and junction temperature for the 844244I-04. Equations and example calculations are also provided. The total power dissipation for the 844244I-04 is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. wire and bond pad temperature remains below 125°C. flow of 1 meter per second and a multi-layer board, the appropriate value is 88°C/W per Table 5 below. Table 5. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection

Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP

REVISION B 10/15/15 15 FEMTOCLOCK ® CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR 844244I-04 DATA SHEET

Ordering Information

Table 8. Ordering Information

FEMTOCLOCK® CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR 16 REVISION B 10/15/15 844244I-04 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B Updated header/footer through the datasheet. Deleted IDT prefix from part number. Features Section - deleted leaded information in the last bullet. Updated Overdriving the XTAL Interface application note. Updated LVDS Driver Termination application note. Ordering Information table - deleted leaded parts rows. 10/15/15

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