844201BKI-45LF | DigiCamel IC Datasheet

Online Datasheet

Read 844201BKI-45LF online.

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 16

Technical content

Features

One differential LVDS output pair
Crystal oscillator interface designed for 18pF, 25MHz parallel resonant crystal
VCO range: 490MHz – 680MHz
RMS phase jitter at 100MHz (12kHz – 20MHz): 0.792ps (typical)
RMS phase jitter at 125MHz (12kHz – 20MHz): 0.773ps (typical)
Full 3.3V output supply mode
PCI Express (2.5Gb/s) and Gen 2 (5Gb/S) jitter compliant
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging Frequency Table Inputs Output Frequency Range (MHz)Crystal Frequency (MHz) M FSEL N Multiplication Value M/N 25 20 1 4 5 125 (default) 25 20 0 5 4 100 5 6 7 8 16 15 14 13 nc XTAL_OUT XTAL_IN FSEL Q nQ VDD nc GND nc nc nc nc nc nc GND Pin Assignment OSC Phase Detector VCO 490MHz - 680MHz M = ÷20 (fixed) N = ÷5 ÷4 (default) Q nQ Pullup XTAL_IN XTAL_OUT FSEL Block Diagram ICS844201I-45 16-Lead VFQFN Top View

ICS844201BKI-45 MAY 27, 2017 2 ©2017 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 13, 14, 15 nc Unused No connect. XTAL_IN Input Crystal oscillator interf ace. XTAL_IN is the input, XTAL_OUT is the output. 4 FSEL Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 5, 16 GND Power Power supply ground. 10 V DD Power Power supply pin. 11, 12 nQ, Q Output Differential outp ut pair. LVDS interface levels.

ICS844201BKI-45 MAY 27, 2017 4 ©2017 Integrated Device Technology, Inc. Table 5. AC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz crystal. NOTE 1: Refer to Phase Noise Plots. the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.

125 MHz

100 MHz

ICS844201I-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR ICS844201BKI-45 MAY 27, 2017 5 ©2017 Integrated Device Technology, Inc. Typical Phase Noise at 100MHz Typical Phase Noise at 125MHz 100MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.792ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz) 125MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.773ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz)

ICS844201I-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR ICS844201BKI-45 MAY 27, 2017 6 ©2017 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup SCOPE Qx nQx 3.3V±10% POWER SUPPL Y +–Float GND VDD 20% 80% 80% 20% tR tF VOD nQ Q VOD 380mV (typical) VDIFF_OUT 760mV (typical) nQ Q

Application Information

The ICS844201I-45 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface

ICS844201I-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR ICS844201BKI-45 MAY 27, 2017 9 ©2017 Integrated Device Technology, Inc. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 3A can be used with either type of output structure. Figure 3B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. LVDS Termination

ICS844201I-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR ICS844201BKI-45 MAY 27, 2017 10 ©2017 Integrated Device Technology, Inc. PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.

ICS844201BKI-45 MAY 27, 2017 11 ©2017 Integrated Device Technology, Inc. Figure 4 shows an example of ICS844201I-45 application schematic. built-in termination are shown in this schematic. Figure 4. ICS844201I-45 Schematic Example

25 MHz

ICS844201BKI-45 MAY 27, 2017 12 ©2017 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS844201I-45. Equations and example calculations are also provided. The total power dissipation for the ICS844201I-45 is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.

Power (core) MAX = VDD_MAX * IDD_MAX = 3.63V * 95mA = 344.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.9°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection

ICS844201I-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR 16©2017 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Te chnology, Inc. (IDT) and its aff iliated companies (herein referred to as “IDT”) reserve the righ t to modify the products and/or specific ations described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of IDT's products for any particular purpose, an implied warran ty of merchantab ility, or non-infringement of the intellectual p roperty rights of others. This documen t is presented only as a guide and does not convey any license under intellectual propert y rights of IDT or any third parties. IDT's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other c ountries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com

Ordering Information

Table 9. Ordering Information

Product Information

844201BKI-45LF specifications and overview.

Summary

FemtoClock Crystal-to-LVDS Clock Generator

Description

FemtoClock Crystal-to-LVDS Clock Generator

Source title 844201BKI-45LF Datasheet(PDF) - Integrated Device Technology

Related Parts

More parts from the same family.

Browse manufacturer