844201

844201 IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• One differential LVDS output
• Crystal oscillator interface designed for 18pF , 25MHz parallel resonant crystal
• VCO range: 490MHz – 680MHz
• RMS phase jitter at 100MHz (12kHz – 20MHz): 0.792ps (typical)
• RMS phase jitter at 125MHz (12kHz – 20MHz): 0.773ps (typical)
• Full 3.3V output supply mode
• PCI Express (2.5Gb/s) and Gen 2 (5Gb/S) jitter compliant
• 0°C to 70°C ambient operating temperature
• Lead-free (RoHS 6) packaging Frequency Table Inputs Output Frequency Range (MHz)Crystal Frequency (MHz) M FSEL N Multiplication Value M/N 25 20 1 4 5 125 (default) 25 20 0 5 4 100 1 GND XTAL_OUT XTAL_IN FSEL Q nQ VDD nc Pin Assignment ICS844201-45

8 Lead TSSOP

4.40mm x 3.0mm x 0.925mmpackage body G Package Top View OSC Phase Detector VCO 490MHz - 680MHz M = ÷20 (fixed) N = ÷5 ÷4 (default) Q nQ Pullup XTAL_IN XTAL_OUT FSEL Block Diagram

ICS844201BG-45 REVISION A OCTOBER 1, 2013 2 ©2013 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 1 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 4 FSEL Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 7, 8 nQ, Q Output Differential outp ut pair. LVDS interface levels.

ICS844201BG-45 REVISION A OCTOBER 1, 2013 3 ©2013 Integrated Device Technology, Inc. Table 4. Crystal Characteristics

ICS844201BG-45 REVISION A OCTOBER 1, 2013 4 ©2013 Integrated Device Technology, Inc. Table 5. AC Characteristics, VDD = 3.3V ± 10%, TA = 0°C to 70°C has been reached under these conditions. NOTE: Characterized using a 25MHz crystal. NOTE 1: Refer to Phase Noise Plots. the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.

125 MHz

100 MHz

ICS844201BG-45 REVISION A OCTOBER 1, 2013 5 ©2013 Integrated Device Technology, Inc. ICS844201-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR Typical Phase Noise at 100MHz Typical Phase Noise at 125MHz 100MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.792ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz) 125MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.773ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz)

ICS844201BG-45 REVISION A OCTOBER 1, 2013 6 ©2013 Integrated Device Technology, Inc. ICS844201-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup SCOPE Qx nQx 3.3V±10% POWER SUPPL Y +–Float GND VDD 20% 80% 80% 20% tR tF VOD nQ Q VOD 380mV (typical) VDIFF_OUT 760mV (typical) nQ Q

ICS844201BG-45 REVISION A OCTOBER 1, 2013 7 ©2013 Integrated Device Technology, Inc. ICS844201-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR

Application Information

The ICS844201-45 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface XTAL_IN XTAL_OUT 18pF Parallel Crystal 27pF 27pF

ICS844201BG-45 REVISION A OCTOBER 1, 2013 10 ©2013 Integrated Device Technology, Inc. ICS844201-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.

ICS844201BG-45 REVISION A OCTOBER 1, 2013 11 ©2013 Integrated Device Technology, Inc. Figure 4 shows an example of ICS844201-45 application schematic. built-in termination are shown in this schematic. Figure 4. ICS844201-45 Schematic Example

25 MHz

ICS844201BG-45 REVISION A OCTOBER 1, 2013 12 ©2013 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS844201-45. Equations and example calculations are also provided. The total power dissipation for the ICS844201-45 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below. Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection

ICS844201BG-45 REVISION A OCTOBER 1, 2013 13 ©2013 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP

ICS844201BG-45 REVISION A OCTOBER 1, 2013 14 ©2013 Integrated Device Technology, Inc. ICS844201-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR

Ordering Information

Table 9. Ordering Information

ICS844201BG-45 REVISION A OCTOBER 1, 2013 15 ©2013 Integrated Device Technology, Inc. ICS844201-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR Revision History Sheet Rev Table Page Description of Change Date A Changed FemtoClock™ to FemtoClock ®. Deleted HyperClock image in the first paragraph. Updated the Overdriving the XTAL Interface note. Updated the LVDS Driver Termination note. Updated the PCI Express Application Note. Power Considerations: Deleted 'NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.' Deleted quantity from Tape & Reel. Deleted Lead-Free note. Deleted disclaimer. 10/1/2013

ICS844201-45 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVDS CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2013. All rights reserved.

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales netcom@idt.com +480-763-2056 We’ve Got Your Timing Solution