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Document overview
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- PDF pages: 14
Technical content
Features
- One differential LVDS output
- Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz – 28.3MHz)
- Output frequency range: 62.5MHz – 170MHz
- VCO range: 500MHz – 680MHz
- RMS phase jitter at 150MHz, using a 25MHz crystal (900kHz – 7.5MHz): 0.45ps (typical)
- Full 3.3V or 2.5V operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) packages
Table 1. Common Configuration Table
8 Lead TSSOP
844071 DATA SHEET
Table 1. Pin Descriptions NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDA Power Analog supply pin. 2 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. 5 FREQ_SEL Input Pullup Frequency select pi n. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential output pair. LVDS interface levels. 8V DD Power Core supply pin.
FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR 3 Rev B 11/17/15 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 10%, TA = 0°C to 70°C Table 3B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 10% or 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.97 3.3 3.63 V VDDA Analog Supply Voltage V DD – 0.12 3.3 3.63 V IDD Power Supply Current 135 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.12 2.5 2.625 V IDD Power Supply Current 120 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current V DD = VIN = 3.63V or 2.625V 5 µA IIL Input Low Current V DD = 3.63V or 2.625V, VIN = 0V -150 µA
Table 4. Crystal Characteristics NOTE: It is not recommended to overdrive the crystal input with an external clock source.
FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR 5 Rev B 11/17/15 Table 5A. AC Characteristics, VDD = 3.3V ± 10%, TA = 0°C to 70° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Refer to the Phase Noise Plot. Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Refer to the Phase Noise Plot. Parameter Symbol Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 62.5 170 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 150MHz, Integration Range: 900kHz – 7.5MHz 0.45 ps 75MHz, Integration Range: 900kHz – 7.5MHz 0.46 ps tR / tF Output Rise/Fall Time 20% to 80% 150 400 ps odc Output Duty Cycle 48 52 % Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 62.5 170 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 150MHz, Integration Range: 900kHz – 7.5MHz 0.56 ps 75MHz, Integration Range: 900kHz – 7.5MHz 0.60 ps tR / tF Output Rise/Fall Time 20% to 80% 150 400 ps odc Output Duty Cycle 48 52 %
Rev B 11/17/15 6 FEMTOCLOCK® CR YSTAL-TO-LVDS CLOCK GENERATOR Typical Phase Noise at 150MHz (3.3V) Raw Phase Noise Data 150MHz RMS Phase Jitter (Random) 900kHz to 7.5MHz = 0.45ps (typical) Noise Power dBc Hz Offset Frequency (Hz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR 7 Rev B 11/17/15 Parameter Measurement Information 3.3V LVDS Output Load Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVDS Output Load Test Circuit Output Duty Cycle/Pulse Width/Period Offset Voltage Setup SCOPE Qx nQx 3.3V±10% POWER SUPPL Y +–Float GND VDD VDDA Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power 20% 80% 80% 20% tR tF VOD nQ Q SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND VDD VDDA nQ Q
Figure 1. Power Supply Filtering
and C2 values can be slightly adjusted for different board layouts. Figure 2. Crystal Input Interface
This section provides information on power dissipation and junction temperature for the 844071. Equations and example calculations are also provided. The total power dissipation for the 844071 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. wire and bond pad temperature remains below 125°C. flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP
Rev B 11/17/15 12 FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR
Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR 13 Rev B 11/17/15 Rev Table Page Description of Change Date AT 8 Added LVCMOS to XTAL Interface section. Ordering Information Table - added lead-free marking. Updated datasheet format. 9/26/07 B T3A - T3B T5A - T5B Pin Assignment - corrected pin 1 from V DD to VDDA. Power Supply Tables - corrected Parameter Column for IDDA from Power to Analog. Crystal Characteristics Table - added note. AC Characteristic Tables - added general note. Parameter Measurement Information - Output Load Test Circuit drawings and Output Rise/Fall Time drawing. Deleted application note, LVCMOS to XTAL Interface. Updated application note, LVDS Driver Termination. Power Considerations - updated Junction Temperature paragraph. Package Dimensions - corrected A1 min. spec from 0.5 to 0.05. Ordering Information - Part/Order Number column: deleted “ICS” prefix; Shipping Packaging column: deleted Tape & Reel count. Deleted disclaimer and updated contact page disclaimer. Updated header/footer format. 10/10/12 Updated data sheet format. 11/17/15
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