8440259EKI-45LFT | DigiCamel IC Datasheet

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ICS8440259I-45 IDT | Alldatasheet

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One differential LVDS output at 156.25MHz or 125MHz Four differential LVDS outputs at 125MHz Three LVCMOS/LVTTL single-ended outputs at 125MHz One LVCMOS/LVTTL single-ended output at 3.90625MHz Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input and PLL bypass from a single select pin VCO range: 560MHz - 690MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.45ps (typical), LVDS outputs RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.45ps (typical), Q0, nQ0 output Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package nQ0 nQ1 nQ2 nQ3 nQ4 Phase Detector VCO 560-690MHz OSC REF_CLK F_SEL nPLL_BYPASS XTAL_IN XTAL_OUT Pulldown 25MHz ÷32 ÷4÷25 Pulldown Pullup 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nQ0 GND nQ1 VDDO_LVDS nQ2 VDDO_LVCMOS GND VDDO_LVCMOS GND GND nQ3 VDDO_LVDS nQ4 GND VDD XTAL_OUT XTAL_IN REF_CLK F_SEL VDD nPLL_BYPASS VDDA GND Block Diagram 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS8440259I-45 Pin Assignment

ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 2 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 Q0, nQ0 Output Differential clock outputs. LVDS interface levels. 17, 21, 32 GND Power Power supply ground. 4, 5 Q1, nQ1 Output Differential clock outputs. LVDS interface levels. 6, 12 V DDO_LVDS Power Output supply pins for Q[0:4], nQ[0:4] LVDS outputs. 7, 8 Q2, nQ2 Output Differential clock outputs. LVDS interface levels. 10, 11 Q3, nQ3 Output Differential clock outputs. LVDS interface levels. 13, 14 Q4, nQ4 Output Differential clock outputs. LVDS interface levels. 16, 27 V DD Power Core supply pins. 18, 20, 22, 24 Q5, Q6, Q7, Q8 Output Single-ended clock outputs.LVCMOS/LVTTL interface levels. 19, 23 V DDO_LVCMOS Power Output supply pins for Q[5:8] LVCMOS outputs. 25 V DDA Power Analog supply pin. 26 nPLL_BYPASS Input Pullup Input select and PLL bypass control pin. See Table 3B. LVCMOS/LVTTL interface levels. 28 F_SEL Input Pulldown Frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels. 29 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. XTAL_OUT Input Crystal oscillator interface. XTAL_O UT is the output, XTAL_IN is the input.

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 3 ©2011 Integrated Device Technology, Inc. Function Tables Table 3A. F_SEL Frequency Select Function Table Table 3B. PLL Bypass and Input Select Function Table Input Output Frequency F_SEL Output Divider Value Q0, nQ0 (MHz) 0 ÷5 125 (default) 1 ÷4 156.25 Inputs nPLL_BYPASS PLL BYPASS Input Selected

0 PLL Bypassed REF_CLK

1 PLL Enabled XTAL_IN, XTAL_OUT (default)

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 4 ©2011 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_LVCMOS = VDDO_LVDS = 3.3V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to VDDO_LVCMOS + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.35 3.3 V DD V VDDO_LVCMOS, VDDO_LVDS Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 105 mA IDDA Analog Supply Current 35 mA IDDO_LVCMOS LVCMOS Output Supply Current 4 mA IDDO_LVDS LVDS Output Supply Current 77 mA

ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 6 ©2011 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = VDDO_LVCMOS = VDDO_LVDS = 3.3V±5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. NOTE 2: Output loaded with 100Ω differential and 15pF loads.

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 7 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 125MHz (Q[0:4]) Typical Phase Noise at 125MHz (Q[5:7]) 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps (typical) Noise Power dBc Hz Offset Frequency (Hz) 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 8 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 156.25MHz (Q0) Noise Power dBc Hz Offset Frequency (Hz) 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps (typical)

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 9 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information LVDS Output Load AC Test Circuit LVCMOS Output Load AC Test Circuit LVDS Output Rise/Fall Time LVDS Output Load AC Test Circuit with 15pF RMS Phase Jitter LVDS Output Rise/Fall Time SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +– Float GND VDD, VDDA VDDO_LVDS SCOPE Qx GND VDDA VDDO_LVCMOS VDD, 1.65V±5% -1.65V±5% 1.65V±5% 30% 70% 70% 30% tR tF VOD Q[0:4] nQ[0:4] SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +– Float GND LVDS 15pF 15pF VDD, VDDA VDDO_LVDS Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power 20% 80% 80% 20% tR tF VOD Q[0:4] nQ[0:4]

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 10 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued LVCMOS Output Rise/Fall Time Single-Ended Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup Differential Output Duty Cycle/Pulse Width/Period Offset Voltage Setup 20% 80% 80% 20% tR tF Q[5:8] Q[5:8] tPERIOD tPW tPERIOD odc = VDDO_CMOS x 100% tPW 100 out out LVDSDC Input VOD/∆ VOD VDD Q[0:4] nQ[0:4] tPW tPERIOD tPW tPERIOD odc = x 100% out out LVDSDC Input ➤ VOS/∆ VOS VDD

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 14 ©2011 Integrated Device Technology, Inc. Schematic Example Figure 4 (on the next page) shows an example of ICS8440259I-45 application schematic. In this example, the device is operated at VDD = VDDO_LVDS = VDDO_LVCMOS = 3.3V. An 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 33pF and C2 = 27pF are recommended for frequency accuracy. Depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8440259I-45 provides separate power supplies to isolate from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set.

ICS8440259EKI-45 REVISION A FEBRUARY25, 2011 16 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8440259I-45. Equations and example calculations are also provided. The total power dissipation for the ICS8440259I-45 is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

Type A: Chamfer on the paddle (near pin 1)
Type C: Mouse bite on the paddle (near pin 1)

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS8440259I-45 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’ s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.

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Product Information

8440259EKI-45LFT specifications and overview.

Summary

FemtoClock Crystal/LVCMOS-to- LVDS/LVCMOS Frequency Synthesizer

Description

FemtoClock Crystal/LVCMOS-to- LVDS/LVCMOS Frequency Synthesizer

Source title 8440259EKI-45LFT Datasheet(PDF) - Integrated Device Technology

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