8440259DK-05LF

8440259D-05 IDT | Alldatasheet

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LVDS/LVCMOS Frequency Synthesizer 8440259D-05 DA T ASHEET 8440259D-05 REVISION A SEPTEMBER 3, 2014 1 ©2014 Integrated Device Technolog y, Inc. nQ0 nQ1 nQ2 nQ3 nQ4 Phase Detector VCO OSC REF_CLK nPLL_BYPASS XTAL_IN XTAL_OUT Pulldown 25MHz ÷32 ÷25 Pullup GENERAL DESCRIPTION The ICS8440259D-05 is a 9 output synthesizer optimized to generate Gigabit and 10 Gigabit Ether-net. Using a 25MHz, 18pF parallel resonant crystal, the device will generate 125MHz and 3.90625MHz clocks with mix-ed LVDS and LVCMOS/LVTTL output levels. The ICS8440259D-05 uses IDT’s 3 rd generations low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8440259D-05 is packaged in a small, 32-pin VFQFN package that is optimum for applications with space limitations.

FEATURES

• Five differential LVDS outputs at 125MHz Three LVCMOS/LVTTL single-ended outputs at 125MHz One LVCMOS/LVTTL single-ended output at 3.90625MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL sin- gle-ended input and PLL bypass from a single select pin
• VCO range: 510MHz - 650MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.41ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package PIN ASSIGNMENT BLOCK DIAGRAM VDDO_LVCMOS GND VDDO_LVCMOS GND nQ0 GND nQ1 VDDO_LVDS nQ2 GND nQ3 VDDO_LVDS nQ4 GND VDD VDDA nPLL_BYPASS VDD nc REF_CLK XTAL_IN XTAL_OUT GND ICS8440259D-05 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16

2 REVISION A 9/3/14

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1, 2 Q0, nQ0 Output Differential clock outputs. LVDS interface levels. 21, 32 GND Power Power supply ground. 4, 5 Q1, nQ1 Output Differential clock outputs. LVDS interface levels. Power Output supply pins for Q[0:4]/nQ[0:4] LVDS outputs. 7, 8 Q2, nQ2 Output Differential clock outputs. LVDS interface levels. 10, 11 Q3, nQ3 Output Differential clock outputs. LVDS interface levels. 13, 14 Q4, nQ4 Output Differential clock outputs. LVDS interface levels. Q7, Q8 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power Output supply pins for Q5:Q8 LVCMOS outputs. 26 nPLL_BYPASS Input Pullup Input select and PLL bypass control pin. See Table 3. LVCMOS/LVTTL interface levels. mode. LVCMOS/LVTTL interface levels. OUT Input Crystal oscillator interface. XTAL_OUT is the output. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 3. PLL BYPASS AND INPUT SELECT FUNCTION TABLE

0 PLL Bypassed REF_CLK

1 PLL Enabled XTAL_IN/XTAL_OUT (default)

8440259D-05 DATA SHEET DATA SHEET

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NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5V Outputs, I O (LVCMOS) -0.5V to V DDO_LVCMOS + 0.5V Outputs, I O (LVDS) Continuous Current 10mA Surge Current 15mA Operating Temperature Range, T A -40°C to +85°C Storage Temperature, T STG -65°C to 150°C Package Thermal Impedance, θ JA 37°C/W (0 mps) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These rat- ings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO_LVCMOS = V DDO_LVDS = 3.3V ± 5%,TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDA Analog Supply Voltage V DD – 0.40 3.3 V DD V V DDO_LVCMOS, V DDO_LVDS Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current Output Not Loaded 120 mA I DDA Analog Supply Current Output Not Loaded 40 mA I DDO_LVCMOS LVCMOS Output Supply Current Output Not Loaded 20 mA I DDO_LVDS LVDS Output Supply Current Output Not Loaded 165 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V DD = V DDO_LVCMOS = 3.3V ± 5%,TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V DD + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current REF_CLK VDD = VIN = 3.465V 150 µA nPLL_BYPASS VDD = VIN = 3.465V 5µ A I IL Input Low Current REF_CLK VDD = 3.465V, VIN = 0V -5 µA nPLL_BYPASS VDD = 3.465V, VIN = 0V -150 µA V OH Output High Voltage Q5:Q8 I OH = -12mA 2.6 V V OL Output Low Voltage Q5:Q8 I OL = 12mA 0.5 V

4 REVISION A 9/3/14

TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6. AC CHARACTERISTICS, V NOTE: TA, Ambient Temperature applied using forced air fl ow. NOTE 1: Please refer to the Phase Noise Plots. NOTE 2: Output loaded with 15pF .

8440259D-05 DATA SHEET DATA SHEET

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NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer TYPICAL PHASE NOISE AT 125MHZ (LVCMOS @ 3.3V) 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz TYPICAL PHASE NOISE AT 125MHZ (LVDS @ 3.3V) Ethernet Filter Raw Phase Noise Data Phase Noise Result by adding Ethernet Filter to raw data Phase Noise Result by adding Ethernet Filter to raw data Raw Phase Noise Data Ethernet Filter

NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer 8440259D-05 DATA SHEET

6 REVISION A 9/3/14

3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PARAMETER MEASUREMENT INFORMATION LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVCMOS OUTPUT RISE/FALL TIMELVDS OUTPUT RISE/FALL TIME 20% 80% 80% 20% tR tF Q[5:8]20% 80% 80% 20% tR tF VOD nQ0:nQ4 Q0:Q4

8440259D-05 DATA SHEET DATA SHEET

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NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer OFFSET VOLTAGE SETUPRMS PHASE JITTER DIFFERENTIAL OUTPUT VOLTAGE SETUP

NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer 8440259D-05 DATA SHEET

8 REVISION A 9/3/14

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8440259D-05 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD , V DDA , V DDO_LVDS and V DDO_LVCMOS should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V DD pin and also shows that V DDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING 1kΩ resistor can be tied from the REF_CLK to ground.

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Figure 3. The XTAL_OUT pin can be left fl oating. The FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE FIGURE 2. CRYSTAL INPUt INTERFACE and were chosen to minimize the ppm error.

10 REVISION A 9/3/14

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION recommended to terminate the unused outputs.

100 Ohm Differiential Transmission Line

FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –S IDE VIEW (DRAWING NOT TO SCALE) Figure 5. The solderable area on the PCB, and the inner edges of pad pattern for the leads to avoid any shorts. achieved when an array of vias is incorporated in the land pattern. Enhance Leadfame Base Package, Amkor Technology.

8440259D-05 DATA SHEET DATA SHEET

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NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8440259D-05. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8440259D-05 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation

• Power (core, LVDS) = V DD_MAX * (I DD + I DDO_LVDS + I DDA ) = 3.465V * (120mA + 165mA + 40mA) = 1126.13mW LVCMOS Output Power Dissipation
• Power (LVCMOS, no load) = V DD_MAX * I DDO_LVCMOS = 3.465V * 20mA = 69.3mW
• Output Impedance R OUT Power Dissipation due to Loading 50Ω to V DDO Output Current I OUT = V DDO_MAX / [2 * (50Ω + R OUT
• Power Dissipation on the R OUT per LVCMOS output Power (R OUT ) = R OUT * (I OUT = 25Ω * (23.1mA) = 13.3mW per output
• Total Power Dissipation on the R OUT Total Power (R OUT
• Dynamic Power Dissipation at 125MHz Power (125MHz) = C PD * Frequency * (V DDO = 15pF * 125MHz * (3.465V) = 22.5mW per output Total Power (125MHz) = 22.5mW * 3 = 67.5mW
• Dynamic Power Dissipation at 3.9MHz Power (3.9MHz) = C PD * frequency * (V DDO = 15pF * 3.90625MHz * (3.465V) = 0.7mW per output Total Power Dissipation
• Total Power = Power (core, LVDS) + Power (LVCMOS, no load) + Total Power (R OUT ) + Total Power (125MHz) + Total Power (3.9MHz) = 1391.51mW

12 REVISION A 9/3/14

TABLE 7. THERMAL RESISTANCE θ JA FOR 32-LEAD VFQFN, FORCED CONVECTION device. The maximum recommended junction temperature is 125°C. and a multi-layer board, the appropriate value is 37°C/W per Table 7. type of board (multi-layer).

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TABLE 8. θ

14 REVISION A 9/3/14

TABLE 9. PACKAGE DIMENSIONS not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page.

8440259D-05 DATA SHEET DATA SHEET

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NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

Revision History

9/3/14 Updated datasheet format Pg 1 Removed Block Diagram VCO limits Removed references to leaded devices Pg 15 Ordering Information - removed leaded devices

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved.