ICS844021-01 IDT | Alldatasheet
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR ICS844021-01 IDT™ / ICS™ LVDS CLOCK GENERATOR 1 ICS844021BG-01 REV. C SEPTEMBER 27, 2007 PRELIMINARY GENERAL DESCRIPTION The ICS844021-01 is an Ethernet Clock Generator and a member of the HiPerClocks TM family of high performance devices from IDT. The ICS844021-01 uses an 18pF parallel resonant crystal over the range of 24.5MHz – 34MHz. For Ethernet appli- cations, a 25MHz crystal is used. The ICS844021-01 has excellent <1ps phase jitter performance, over the 1.875MHz – 20MHz integration range. The ICS844021-01 is packaged in a small 8-pin TSSOP , making it ideal for use in systems with limited board space.
FEATURES
- One Differential LVDS output
- Crystal oscillator interface, 18pF parallel resonant crystal (24.5MHz – 34MHz)
- Output frequency range: 122.5MHz – 170MHz
- VCO range: 490MHz – 680MHz
- RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.32ps (typical) @ 3.3V
- 3.3V or 2.5V operating supply
- 0°C to 70°C ambient operating temperature
- Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS ICS844021-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VDDA GND XTAL_OUT XTAL_IN VDD Q nQ OE BLOCK DIAGRAM OSC Phase Detector VCO 490MHz - 680MHz M = ÷20 (fixed) N = ÷4 (fixed) XTAL_IN XTAL_OUT OE Q nQ Pullup COMMON CONFIGURATION TABLE - Gb ETHERNET PIN ASSIGNMENT stupnI ycneuqerFtuptuO )zHM()zHM(ycneuqerFlatsyrCM N noitacilpitluM N/MeulaV 520 24 5 5 21 666.620 24 5 3 3.331 33.330 24 5 6 6.661 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS
IDT™ / ICS™ LVDS CLOCK GENERATOR 3 ICS844021BG-01 REV. C SEPTEMBER 27, 2007 ICS844021-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Char- acteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, TA = 0°C TO 70°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θJA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 531.33 .35 64.3V V ADD egatloVylppuSgolanAV DD 80.0–3 .3V DD V I DD tnerruCylppuSrewoP 55A m I ADD tnerruCylppuSgolanA 8A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 573.25 .25 26.2V V ADD egatloVylppuSgolanAV DD 80.0–5 .2V DD V I DD tnerruCylppuSrewoP 25A m I ADD tnerruCylppuSgolanA 8A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI V DD V3.3=2 V DD 3.0+V V DD V5.2=7 .1V DD 3.0+V V LI egatloVwoLtupnI V DD V3.3=3 .0-8 .0V V DD V5.2=3 .0-7 .0V I HI tnerruChgiHtupnIV DD V= NI V526.2roV564.3=5 A µ I LI tnerruCwoLtupnIV DD V,V526.2roV564.3= NI V0=0 51-A µ
TABLE 4. CRYSTAL CHARACTERISTICS
IDT™ / ICS™ LVDS CLOCK GENERATOR 5 ICS844021BG-01 REV. C SEPTEMBER 27, 2007 ICS844021-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY TYPICAL PHASE NOISE AT 125MHZ @ 3.3V 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.32ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding Ethernet Filter to raw data Raw Phase Noise Data Ethernet Filter TYPICAL PHASE NOISE AT 125MHZ @ 2.5V OFFSET FREQUENCY (HZ) 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.32ps (typical) NOISE POWER dBc Hz Phase Noise Result by adding Ethernet Filter to raw data Raw Phase Noise Data Ethernet Filter
IDT™ / ICS™ LVDS CLOCK GENERATOR 6 ICS844021BG-01 REV. C SEPTEMBER 27, 2007 ICS844021-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD Q nQ 100 out out LVDSDC Input VOD/Δ VOD VDD out out LVDSDC Input ➤ VOS/Δ VOS VDD VDD VDD Clock Outputs 20% 80% 80% 20% tR tF VOD DIFFERENTIAL OUTPUT VOLTAGE SETUP Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tPW tPERIOD tPW tPERIOD odc = x 100% SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND LVDS SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDD VDDA VDD VDDA
is shown in Figure 3. The XTAL_OUT pin can be left floating. series resistance (Rs) equals the transmission line impedance. FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
Equations and example calculations are also provided. = 3.3V + 5% = 3.465V, which gives worst case results.
- Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA_MAX 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 8-LEAD TSSOP, FORCED CONVECTION
TABLE 7. θ
TABLE 8. PACKAGE DIMENSIONS
TABLE 9. ORDERING INFORMATION
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Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA ICS844021-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY