ICS844011 IDT | Alldatasheet

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Features

• One differential LVDS clock output pair • Crystal interface designed for 18pF parallel resonant crystals • VCO range: 490MHz – 680MHz • RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.97ps (typical) • RMS phase jitter @ 100MHz, (637kHz - 10MHz): 0.77ps (typical) • Full 3.3V or 2.5V operating supply • Available in lead-free (RoHS 6) package • 0°C to 70°C ambient operating temperature Common Configuration Table – Fibre Channel Inputs Output Frequency (MHz)Crystal Frequency (MHz) M N Mu ltiplication Value M/N 26.5625 24 6 4 106.25 25 24 6 4 100 OSC Phase Detector VCO 490MHz - 680MHz M = ÷24 (fixed) N = ÷6 (fixed) Q nQ OE XTAL_IN XTAL_OUT Pullup 1 VDDA GND XTAL_OUT XTAL_IN VDD Q nQ OE Block Diagram Pin Assignment ICS844011 8-lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View

ICS844011AG REVISION A AUGUST 27, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. OE Control Function Table 1V DDA Power Analog power supply. 2G ND P ower Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential clock output. LVDS interface levels. 8V DD Power Core supply pin. 0 Output Q, nQ pair is dis abled in high-impedance state. 1 (default) Output Q, nQ is enabled.

ICS844011AG REVISION A AUGUST 27, 2012 3 ©2012 Integrated Device Technology, Inc. ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C Table 4C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Input 0V to VDD -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.12 3.3 V DD V IDD Power Supply Current 108 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage VDD – 0.12 2.5 V DD V IDD Power Supply Current 102 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current OE V DD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE V DD = 3.465V or 2.625V, VIN = 0V -150 µA

ICS844011AG REVISION A AUGUST 27, 2012 4 ©2012 Integrated Device Technology, Inc. Table 5. Crystal Characteristics

ICS844011AG REVISION A AUGUST 27, 2012 5 ©2012 Integrated Device Technology, Inc. ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR AC Characteristics Table 6A. AC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to the phase noise plot. Table 6B. AC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 100 106.25 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 106.25MHz, Integration Range: 637kHz – 10MHz 0.97 ps 100MHz, Integration Range: 637kHz – 10MHz 0.77 ps tR / tF Output Rise/Fall Time 20% to 80% 150 400 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 100 106.25 MHz tjit(Ø) RMS Phase Jitter (Random) 106.25MHz, Integration Range: 637kHz – 10MHz 1.26 ps 100MHz, Integration Range: 637kHz – 10MHz 0.98 ps tR / tF Output Rise/Fall Time 20% to 80% 150 400 ps odc Output Duty Cycle 48 52 %

ICS844011AG REVISION A AUGUST 27, 2012 6 ©2012 Integrated Device Technology, Inc. ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR Typical Phase Noise at 106.25MHz (3.3V) Noise Power dBc Hz Offset Frequency (Hz)

ICS844011AG REVISION A AUGUST 27, 2012 7 ©2012 Integrated Device Technology, Inc. ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information 3.3V LVDS Output Load Test Circuit Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup Output Rise/Fall Time 2.5V LVDS Output Load Test Circuit RMS Phase Jitter Offset Voltage Setup SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +– Float GND VDD VDDA tPW tPERIOD tPW tPERIOD odc = x 100% nQ Q 100 out out DC Input VOD/∆ VOD VDD 20% 80% 80% 20% tR tF VOD nQ Q SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +– Float GND VDD VDDA Offset Frequencyf1 f2 Phase Noise Plot Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter = Noise Power 2 * * ƒ 1 * out out LVDSDC Input ä VOS/∆ VOS VDD

ICS844011AG REVISION A AUGUST 27, 2012 11 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS844011. Equations and example calculations are also provided. The total power dissipation for the ICS844011 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. maximum recommended junction temperature for HiPerClockS devices is 125°C. a multi-layer board, the appropriate value is 129.5°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection

ICS844011AG REVISION A AUGUST 27, 2012 12 ©2012 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 8-lead TSSOP

ICS844011AG REVISION A AUGUST 27, 2012 13 ©2012 Integrated Device Technology, Inc. ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Ordering Information

Table 10. Ordering Information

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’ s sole discretion. All information in this document, including descriptions of product features and performance, is subj ect to change without notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to sig- nificantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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