844008I-46

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844008I-46 REVISION A 11/6/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 844008I-46 is a 10Gb Ethernet Clock Generator and a member of the HiPerClocks™ family of high performance devices from IDT. The 844008I-46 can synthesize 156.25MHz or 100MHz with a 25MHz crystal. It has a total of 8 LVDS outputs. The 844008I-46 has excellent phase jitter performance and is packaged in a 32 Lead VFQFN package , making it ideal for use in systems with limited board space.

FEATURES

 Eight differential LVDS outputs  Crystal oscillator interface designed for 18pF parallel resonant crystals  Supports the following output frequencies: 156.25MHz or 100MHz  VCO frequency: 625MHz or 600MHz  RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.45ps (typical)  Full 2.5V supply mode  -40°C to 85°C ambient operating temperature  Available in lead-free (RoHS 6) packages  For functional replacement part use 8T49N285 PIN ASSIGNMENT Phase Detector VCO 625MHz or 600MHz FB = ÷25 or ÷24 OSC Q0:Q7 nQ0:nQ7 XTAL_IN XTAL_OUT FREQ_SEL OE Pulldown Pullup 25MHz or BLOCK DIAGRAM nc OE GND nQ7 V DDO nQ6 nQ0 GND nQ1 VDDO nQ2 nQ3 GND nQ4 VDDO nQ5 VDDA FREQ_SEL VDD nc nc XTAL_IN XTAL_OUT GND ICS844008I-46 32-Lead VFQFN 5mm x 5mm x 0.925mm pack- age body K Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 FREQUENCY SELECT FUNCTION TABLE Input FB Divider Output Divider VCO (MHz) Output Frequency (MHz) XTAL Frequency (MHz) FREQ_SEL 25 0 ÷25 ÷4 625 156.25 (default) 25 1 ÷24 ÷6 600 100

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TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. OE FUNCTION TABLE

1 Enabled (default)

0 Hi-Z

1, 2 Q0, nQ0 Output Differential output pair. LVDS interface levels. 3, 11, 22, 32 GND Power Power supply ground. 4, 5 Q1, nQ1 Ouput Differential output pair. LVDS interface levels. 7, 8 Q2, nQ2 Output Differential output pair. LVDS interface levels. 9, 10 Q3, nQ3 Output Differential output pair. LVDS interface levels. 12, 13 Q4, nQ4 Output Differential output pair. LVDS interface levels. 15, 16 Q5, nQ5 Output Differential output pair. LVDS interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVDS interface levels. 20, 21 Q7, nQ7 Output Differential output pair. LVDS interface levels. are enabled. LVCMOS/LVTTL interface levels. See Table 3. 24, 28, 29 nc Unused No connect. 26 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

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TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V DD = V DDO ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5V Outputs, I O (LVDS) Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θ JA 37°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V DD + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current OE V DD = V IN = 2.625 5 µA FREQ_SEL V DD = V IN = 2.625 150 µA I IL Input Low Current OE V DD = 2.625V, V IN = 0V -150 µA FREQ_SEL V DD = 2.625V, V IN = 0V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 2.375 2.5 2.625 V V DDA Analog Supply Voltage V DD – 0.25 2.5 V DD V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 60 mA I DDA Analog Supply Current 25 mA I DDO Output Supply Current 140 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V OD Differential Output Voltage 247 340 454 mV Δ V OD V OD Magnitude Change 50 mV V OS Offset Voltage 1.10 1.25 1.375 V Δ V OS V OS Magnitude Change 50 mV TABLE 4C. LVDS DC CHARACTERISTICS, V DD = V DDO

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TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6. AC CHARACTERISTICS, V NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.

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TYPICAL PHASE NOISE AT 156.25MHZ 156.25MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.45ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER Ethernet Filter Raw Phase Noise Data ➤Phase Noise Result by adding Ethernet Filter to raw data TYPICAL PHASE NOISE AT 100MHZ OFFSET FREQUENCY (HZ) 100MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.52ps (typical) 10Gb Ethernet Filter Raw Phase Noise Data ➤Phase Noise Result by adding a 10Gb Ethernet Filter to raw data

FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR 844008I-46 DATA SHEET

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PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEWCYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIMEOUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

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DIFFERENTIAL OUTPUT VOLTAGE SETUPOFFSET VOLTAGE SETUP PARAMETER MEASUREMENT INFORMATION, CONTINUED

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter per- formance, power supply isolation is required. The 844008I-46 provides separate power supplies to isolate any high switch- ing noise from the outputs to the internal PLL. V DD , V DDA , and V DDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V CC pin and also shows that V DDA requires that an additional 10 Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING

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FIGURE 2. CRYSTAL INPUt INTERFACE resonant crystal and were chosen to minimize the ppm error. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE resistance is not required but can be added for additional protection.

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FIGURE 5. TYPICAL LVDS DRIVER TERMINATION

100 Ohm Differential Transmission Line

FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) and the inner edges of pad pattern for the leads to avoid any shorts. achieved when an array of vias is incorporated in the land pattern. Enhance Leadfame Base Package, Amkor Technology.

FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR 844008I-46 DATA SHEET

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Figure 6 shows an example of 844008I-46 application schematic. In this example, the device is operated at V DD = V DDO = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended To Logic Input pins 10uF nQ2 OE nQ4 VDDO Set Logic Input to '0' To Logic Input pins FREQ_SEL Zo = 50 Ohm Zo = 50 Ohm nQ7 nQ0 27pF RD2 nQ6 V DD= V DDO=3.3V VDD nQ1 100 25MHz VDD VDDO GND nQ3 RU2 Not Install VDDO 27pF 0.1uF Set Logic Input to '1' Zo = 50 Ohm Logic Control Input Examples 0.01u VDDA nQ5 nQ6 0.1uF RD1 Not Install RU1 0.1uF Zo = 50 Ohm 0.1uFVDD nQ7 18pF VDD ICS844008I-46 nQ0 GND nQ1 VDDO nQ2 nQ3 GND nQ4 VDDO nQ5 nQ6 VDDO nQ7 GND OE nc GND XTAL_OUT XTAL_IN nc nc VDD FREQ_SEL VDDA 0.1uF Alternate LVDS Termination for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVDS for receiver without built-in termination are shown in this schematic. F IGURE 6. 844008I-46 SCHEMATIC LAYOUT

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This section provides information on power dissipation and junction temperature for the 844008I-46. Equations and example calculations are also provided. = 2.5V + 5% = 2.625V, which gives worst case results.

• Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA_MAX + I DDO_MAX ) = 2.625V * (60mA + 25mA + 140mA) = 590.625mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.591W * 37°C/W = 106.8°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).

TABLE 7. THERMAL RESISTANCE θJA FOR 32-LEAD VFQFN, FORCED CONVECTION

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TABLE 8. θ

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TABLE 9. PACKAGE DIMENSIONS package dimensions are in Table 9 below.

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TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

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Rev Table Page Description of Change Date A 1 Product Discontinuation Notice - Last time buy expires November 2, 2016. PDN# CQ-15-05 11/6/15

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.