ICS844008I IDT | Alldatasheet

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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER ICS844008I-01 IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 1 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 GENERAL DESCRIPTION The ICS844008I-01 is an 8 output LVDS Synthesizer optimized to generate GbE/10GbE reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. Using a 25MHz parallel resonant crystal, the following frequencies can be generated based on the F_SEL pin: 125MHz or 156.25MHz. The ICS844008I-01 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting GbE/10GbE jitter requirements. The ICS844008I-01 is packaged in a 32-pin TQFP or 32 VFQFN packages.

FEATURES

 Eight LVDS outputs  Crystal oscillator interface  Supports the following output frequencies: 125MHz or 156.25MHz  VCO: 625MHz  RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.38ps (typical)  Full 3.3V supply mode  -40°C to 85°C ambient operating temperature  Available in lead-free (RoHS 6) packages HiPerClockS™ ICS PIN ASSIGNMENT FREQUENCY SELECT FUNCTION TABLE 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 QA0 nQA0 V DD QA1 nQA1 GND QA2 nQA2 MR nQB0 QB0 GND V DD nQA3 QA3 F_SEL VDDA nPLL_SEL VDD OEB GND XTAL_OUT XTAL_IN OEA ICS844008I-01 32-Lead TQFP, E-Pad 7mm x 7mm x 1.0mm package body Y Package Top View QB3 nQB3 V DD QB2 nQB2 GND QB1 nQB1 Phase Detector VCO 625MHz (w/25MHz Reference) M = ÷25 (fixed) OSC QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 nPLL_SEL XTAL_IN XTAL_OUT OEB F_SEL MR Pulldown OEA Pullup Pulldown Pullup Pullup 25MHz BLOCK DIAGRAM tupnI )zHM(ycneuqerFtuptuO)zHM(ycneuqerFtupnIL ES_Fe ulaVrediviDMe ulaVrediviDN zHM520 5 24 5 2.651 zHM521 5 25 ) tluafed(521 ICS844008I-01 32-Lead TQFP, E-Pad 7mm x 7mm x 1.0mm package body Y Package Top View ICS844008I-01 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 3 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θJA 32 TQFP , E-Pad 32.2°C/W (0 mps)

32 VFQFN 37°C/W (0 mps)

Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnIV DD V3.3=2 V DD 3.0+V V LI egatloVwoLtupnIV DD V3.3=3 .0-8 .0V I HI tupnI tnerruChgiH LES_LLPn,RMV DD V= NI V564.3=0 51A µ LES_F,BEO,AEOV DD V= NI V564.3=5 A µ I LI tupnI tnerruCwoL LES_LLPn,RMV DD V,V564.3= NI V0=5 -A µ LES_F,BEO,AEOV DD V,V564.3= NI V0=0 51-A µ TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 531.33 .35 64.3V V ADD egatloVylppuSgolanAV DD 02.0–3 .3V DD V I DD tnerruCylppuSrewoP 572A m I ADD tnerruCylppuSgolanA 02A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DO egatloVtuptuOlaitnereffiD 5230 55V m Δ V DO V DO egnahCedutingaM 05V m V SO egatloVtesffO2 .13 .15 .1V Δ V SO V SO egnahCedutingaM 05V m

TABLE 6. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C TABLE 5. CRYSTAL CHARACTERISTICS

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 5 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ 125MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.38ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER Raw Phase Noise Data TYPICAL PHASE NOISE AT 156.25MHZ 156.25MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.42ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER Raw Phase Noise Data Gigabit Ethernet Filter Phase Noise Result by adding a Gigabit Ethernet Filter to raw data Phase Noise Result by adding a Gigabit Ethernet Filter to raw data Gigabit Ethernet Filter

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 6 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT t sk(o) Qy Qx nQy nQx Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tPW tPERIOD tPW tPERIOD odc = x 100% CYCLE-TO-CYCLE JITTEROUTPUT SKEW SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS OUTPUT RISE/FALL TIMEOUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1

1000 Cycles

nQA0:nQA3, nQB0:nQB3 20% 80% 80% 20% tR tF VOD VDDA VDD QA0:QA3, QB0:QB3 nQA0:nQA3, nQB0:nQB3 QA0:QA3, QB0:QB3 nQA0:nQA3, nQB0:nQB3 QA0:QA3, QB0:QB3 DIFFERENTIAL OUTPUT VOLTAGE SETUPOFFSET VOLTAGE SETUP out out LVDSDC Input ➤ VOS/Δ VOS VDD 100 out out LVDSDC Input VOD/Δ VOD VDD

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 7 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The I CS844008I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and V DDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V DD pin and also shows that V DDA requires that an additional10 Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING protection. A 1k Ω resistor can be used. between the differential pair.

FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) Figure 5. The the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. land pattern must be connected to ground through these vias. FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

100 Ohm Differential Transmission Line

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 12 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS844008I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844008I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results.

  • Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA_MAX ) = 3.465V * (275mA + 20mA) = 1022.175mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.022W * 37°C/W = 122.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (multi-layer). TABLE 7A. THERMAL RESISTANCE θθθθθJA FOR 32-LEAD TQFP, E-PAD FORCED CONVECTION θθθθθJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 32.2°C/W 26.3°C/W 24.7°C/W TABLE 7B. THERMAL RESISTANCE θθθθθJA FOR 32-LEAD VFQFN, FORCED CONVECTION θθθθθJA vs. Air Flow (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 13 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for ICS844008I-01 is: 2652 TABLE 8A. θ JA VS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD θθθθθJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 32.2°C/W 26.3°C/W 24.7°C/W TABLE 8B. θ JA VS. AIR FLOW TABLE FOR 32 LEAD VFQFN θθθθθJA vs. Air Flow (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 14 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD TABLE 9A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-026 -HD VERSION EXPOSED PAD DOWN NOITAIRAVCEDEJ SRETEMILLIMNISNOISNEMIDLLA LOBMYS DH-ABA MUMINIML ANIMONM UMIXAM N 23 A --- -0 2.1 1A 50.00 1.05 1.0 2A 59.00 .15 0.1 b 03.05 3.00 4.0 c 90.0- -0 2.0 D CISAB00.9 1D CISAB00.7 2D .feR06.5 E CISAB00.9 1E CISAB00.7 2E .feR06.5 e CISAB08.0 L 54.00 6.05 7.0 θθθθθ 0° -- 7° ccc --- -0 1.0 3D&3D 0.35 .30 .4

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 15 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN TABLE 9B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-220 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This draw- ing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9 below. NOITAIRAVCEDEJ )4-/2-DHHV(SRETEMILLIMNISNOISNEMIDLLA LOBMYSm uminiMm umixaM N 23 A 08.00 .1 1A 05 0.0 3A ecnerefeR52.0 b 81.00 3.0 e CISAB05.0 ND 8 NE 8 E,D CISAB0.5 2E,2D 0.33 .3 L 03.00 5.0

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 10. ORDERING INFORMATION

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 17 ICS844008AYI-01 REV. B NOVEMBER 21, 2008 ICS844008I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER TEEHSYROTSIHNOISIVER veRe lbaTe gaPe gnahCfonoitpircseDe taD B 6T4 otmumimxamsp57morftimilrettijelcyc-ot-elcycdetcerroc-elbaTscitsiretcarahCCA .mumixamsp52 80/31/5 B 01. tuoyaLcitamehcSdeddA .teehsatadehttuohguorhtegakcapNFQFV23deddA 80/12/11

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA