844004I-104 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 19
Technical content
Features
- Four differential LVDS outputs
- Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
- Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
- VCO range: 560MHz - 680MHz
- RMS phase jitter at 212.5MHz (637kHz – 10MHz), using a 26.5625MHz crystal: <1ps (typical)
- Full 3.3V or 2.5V output supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) packages Frequency Table Inputs Output Frequency (MHz) Input Frequency (MHz) F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Divider Value 26.5625 0 0 24 3 8 212.5 (default) 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 23.4375 0 0 24 3 8 187.5 (default) Phase Detector VCO 637.5MHz (w/26.5625MHz Reference) M = 24 (fixed) F_SEL[1:0] 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 OSC F_SEL[1:0] nPLL_SEL nXTAL_SEL MR REF_CLK XTAL_IN XTAL_OUT nQ0 nQ1 nQ2 nQ3 Pulldown Pulldown Pulldown Pulldown Pulldown 26.5625MHz 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nQ0 MR nPLL_SEL nc nc nc nc nQ3 GND nc nc nXTAL_SEL REF_CLK GND VDDA F_SEL0 VDD F_SEL1 XTAL_OUT XTAL_IN nc nc nQ1 nc nc nQ2 VDDO VDDO Block Diagram Pin Assignment ICS844004I-104
32 Lead VFQFN
5mm x 5mm x 0.925mm package body K Package Top View
Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 Q0, nQ0 Output Differ ential output pair. LVDS interface levels.
3 MR Input Pulldown
to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Bypass). LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 11 V DD Power Core supply pin. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 17, 22 GND Power Power supply ground. 18 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 23, 24 nQ3, Q3 Output Diffe rential output pair. LVDS interface levels. 25, 32 V DDO Power Output supply pins. 26, 27 Q2, nQ2 Output Differential outp ut pair. LVDS interface levels. 30, 31 nQ1, Q1 Output Diffe rential output pair. LVDS interface levels.
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 3 Rev A 6/11/15 844004I-104 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 42.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 105 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 120 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.10 2.5 V DD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 100 mA
Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 5 Rev A 6/11/15 844004I-104 DATA SHEET Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 35 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 3 212.5MHz, (637kHz - 10MHz) 0.73 ps 159.375MHz, (637kHz - 10MHz) 0.78 ps 106.25MHz, (637kHz -10MHz) 0.92 ps 53.125MHz, (637kHz - 10MHz) 0.95 ps 187.5MHz, (637kHz - 10MHz) 0.75 ps t R / tF Output Rise/Fall Time 20% to 80% 250 500 ps odc Output Duty Cycle Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 35 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 3 212.5MHz, (637kHz - 10MHz) 0.72 ps 159.375MHz, (637kHz - 10MHz) 0.88 ps 106.25MHz, (637kHz -10MHz) 0.89 ps 53.125MHz, (637kHz - 10MHz) 0.96 ps 187.5MHz, (637kHz - 10MHz) 0.74 ps t R / tF Output Rise/Fall Time 20% to 80% 250 550 ps odc Output Duty Cycle
Rev A 6/11/15 6 FEMTOCLOCK® CRYSTAL -TO-LVDS FREQUENCY SYNTHESIZER 844004I-104 DATA SHEET Typical Phase Noise at 106.25MHz (3.3V) Typical Phase Noise at 212.5MHz (3.3V) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 106.25MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.89ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 212.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.72ps (typical) Noise Power dBc Hz Off F (H )
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 7 Rev A 6/11/15 844004I-104 DATA SHEET Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Skew Output Rise/Fall Time 2.5V LVDS Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period 3.3V ±5% VDD, VDDO VDDA Qx nQx Qy nQy 20% 80% 80% 20% tR tF VOD nQ[0:3] QA[0:3} SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +– Float GND VDD, VDDO VDDA Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ[0:3] QA[0:3}
capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering
protection, a 1k resistor can be tied from the REF_CLK to ground. at the receiver and a 100 differential transmission line environment. Figure 4. Typical LVDS Driver Termination
and the inner edges of pad pattern for the leads to avoid any shorts. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
This section provides information on power dissipation and junction temperature for the 844004I-104. Equations and example calculations are also provided. The total power dissipation for the 844004I-104 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 42.4°C/W per Table 7 below. Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
Table 9. Package Dimensions for 32-Lead VFQFN package dimensions are in Table 9.
- Type A: Chamfer on the paddle (near pin 1)
- Type C: Mouse bite on the paddle (near pin 1)
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 16 Rev A 6/11/15 844004I-104 DATA SHEET
Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 17 Rev A 6/11/15 844004I-104 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date A T5A - T5B T10 AC Characteristics Tables - added Thermal Note. Updated Overdriving the Crystal Interface section. Updated LVDS Driver Termination section. Updated Package Outline section. Ordering Information Table - corrected marking. Updated header/footer of datasheet. 12/15/10 A T10 16 Ordering Information - removed leaded devices. Features Section - removed reference to leaded devices. Updated data sheet format. 6/11/15
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